Brian T. Murray - researchr alias

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Viewing Publication 1 - 25 from 25

2005

Dependable communication synthesis for distributed embedded systemsNagarajan Kandasamy, John P. Hayes, Brian T. Murray. ress, 89(1):81-92, 2005. [doi]

Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator DiagnosisNagarajan Kandasamy, John P. Hayes, Brian T. Murray. tpds, 16(3):258-270, 2005. [doi]

2003

Dependable Communication Synthesis for Distributed Embedded SystemsNagarajan Kandasamy, John P. Hayes, Brian T. Murray. safecomp 2003: 275-288 [doi]

Low-Cost On-Line Fault Detection Using Control Flow AssertionsRajesh Venkatasubramanian, John P. Hayes, Brian T. Murray. iolts 2003: 137-143 [doi]

2002

Time-Constrained Failure Diagnosis in Distributed Embedded SystemsNagarajan Kandasamy, John P. Hayes, Brian T. Murray. dsn 2002: 449-458 [doi]

2000

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring countersKrishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar. tvlsi, 8(5):633-636, 2000. [doi]

Providing convincing evidence of safety in X-by-wire automotive systemsBarbara J. Czerny, Joseph G. D'Ambrosio, Brian T. Murray. hase 2000: 189-192 [doi]

1999

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring CountersKrishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar. vts 1999: 22-27 [doi]

Deterministic Built-in Pattern Generation for Sequential CircuitsVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray. et, 15(1-2):97-114, 1999. [doi]

Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded SystemsNagarajan Kandasamy, John P. Hayes, Brian T. Murray. srds 1999: 212-221 [doi]

1998

Online BIST for Embedded SystemsHussain Al-Asaad, Brian T. Murray, John P. Hayes. dt, 15(4):17-24, 1998. [doi]

Scalable Test Generators for High-Speed Datapath CircuitsHussain Al-Asaad, John P. Hayes, Brian T. Murray. et, 12(1-2):111-125, 1998. [doi]

Design of built-in test generator circuits using width compressionKrishnendu Chakrabarty, Brian T. Murray. tcad, 17(10):1044-1051, 1998. [doi]

Optimal Zero-Aliasing Space Compaction of Test ResponsesKrishnendu Chakrabarty, Brian T. Murray, John P. Hayes. TC, 47(11):1171-1187, 1998.

Huffman encoding of test sets for sequential circuitsVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray. tim, 47(1):21-25, 1998. [doi]

Built-In Self Testing of Sequential Circuits Using Precomputed Test SetsVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray. vts 1998: 418-423 [doi]

1997

Test Width Compression for Built-In Self TestingKrishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray. itc 1997: 328-337

1996

Testing ICs: Getting to the Core of the ProblemBrian T. Murray, John P. Hayes. Computer, 29(11):32-38, 1996.

1995

Optimal Space Compaction of Test ResponsesKrishnendu Chakrabarty, Brian T. Murray, John P. Hayes. itc 1995: 834-843

1994

Codesign of architectures for automotive powertrain modulesXiaobo Hu, Joseph G. D'Ambrosio, Brian T. Murray, Dah-Lain Tang. micro, 14(4):17-25, 1994. [doi]

Hierarchical testing using precomputed tests for modulesBrian T. Murray. PhD thesis, University of Michigan, USA, 1994. [doi]

1991

Test Propagation Through Modules and CircuitsBrian T. Murray, John P. Hayes. itc 1991: 748-757

1990

Hierarchical test generation using precomputed tests for modulesBrian T. Murray, John P. Hayes. tcad, 9(6):594-603, 1990. [doi]

1989

High-Level Test Generation for VLSIDebashis Bhattacharya, Brian T. Murray, John P. Hayes. Computer, 22(4):16-24, 1989.

1988

Hierarchical Test Generation Using Precomputed Tests for ModulesBrian T. Murray, John P. Hayes. itc 1988: 221-229

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