Table of Contents

• Concurrent Engineering: Creating Designs That Are Faster, Better and Available SoonerPhil Robinson. 19
• Built-In Self-Test Considerations in a High-Performance, General-Purpose ProcessorSudha Sarma. 21-27
• Production Experience with Built-In Self-Test in the IBM ES/9000 SystemPaul H. Bardell, Michael J. Lapointe. 28-36
• Built-In Self-Test of the VLSI Content Addressable FilestoreRichard Illman, Terry Bird, George Catlow, Steve Clarke, Len Theobald, Gil Willetts. 37-46
• Built-In Self-Test for High-Speed Data-Path CircuitryCharles E. Stroud. 47-56
• A Common Approach to Test Generation and Hardware Verification Based on Temporal LogicThomas Kropf, Hans-Joachim Wunderlich. 57-66
• Fast Sequential ATPG Based on Implicit State EnumerationHyunwoo Cho, Gary D. Hachtel, Fabio Somenzi. 67-74
• A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal StatesToshinobu Ono, Masaaki Yoshida. 75-82
• A Sequential Test Generator with Explicit Elimination of Easy-to-Test FaultsTsu-Wei Ku, Wei-Kong Chia. 83-87
• Test Generation: A Boundary Scan Implementation for Module Interconnect TestingMark F. Lefebvre. 88-95
• Maximal Diagnosis for Wiring NetworksJung-Cheun Lien, Melvin A. Breuer. 96-105
• Testing the Integrity of the Boundary Scan Test InfrastructureFrans de Jong, Frank van der Heyden. 106-112
• A Design-for-Testability Architecture for Multichip ModulesKenneth E. Posse. 113-121
• Testability Features of the 68HC16Z1Jose A. Lyon, Mike Gladden, Eytan Hartung, Eric Hoang, K. Raghunathan. 122-130
• Implementing Boundary-Scan and Pseudo-Random BIST in an Asynchronous Transfer Mode SwitchP. Thorel, J. L. Rainard, A. Botta, A. Chemarin, J. Majos. 131-139
• Two Fault Injection Techniques for Test of Fault Handling MechanismsJohan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin. 140-149
• Test Grading the 68332Tony Cheng, Eric Hoang, David Rivera, Alan Haedge, Jamie Fontenot, Glenn Carson. 150-156
• A Layout Driven Design for Testability Technique for MOS VLSI CircuitsSungho Kim, Prithviraj Banerjee, Srinivas Patil. 157-165
• The Best Flip-Flops to ScanMiron Abramovici, James J. Kulikowski, Rabindra K. Roy. 166-173
• Partitioning Hierarchical Designs for TestabilityMagdy S. Abadir, Joe Newman, Desmond D Souza, Steve Spencer. 174-183
• Search State Equivalence for Redundancy Identification and Test GenerationJohn Giraldi, Michael L. Bushnell. 184-193
• COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial CircuitsIrith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy. 194-203
• Minimal Test Sets for Combinatorial CircuitsGert-Jan Tromp. 204-209
• Estimating the Quality of Manufactured Digital Sequential CircuitsDharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal. 210-217
• A Generic Method to Develop a Defect Monitoring System for IC ProcessesEric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess. 218-227
• On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield PredictionAdit D. Singh, C. Mani Krishna. 228-237
• Coupling Electron-Beam Probing with Knowledge-Based Fault LocalizationM. Marzouki, J. Laurent, Bernard Courtois. 238-247
• On the Integration of Design and Manufacturing for Improved TestabilityRafic Z. Makki, Kasra Daneshvar, Farid Tranjan, Richard Greene. 248-255
• An Approach to Chip-Internal Current Monitoring and Measurement Using an Electron Beam TesterKlaus Helmreich, Peter Nagel, Werner Wolz, Klaus D. Müller-Glaser. 256-262
• Robustly Scan-Testable CMOS Sequential CircuitsBong-Hee Park, Premachandran R. Menon. 263-272
• Achieving Complete Delay Fault Testability by Extra InputsIrith Pomeranz, Sudhakar M. Reddy. 273-282
• A Methodology for Designing Optimal Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. 283-291
• Resistive Shorts Within CMOS GatesHong Hao, Edward J. McCluskey. 292-301
• The Behavior and Testing Implications of CMOS IC Logic Gate Open CircuitsChristopher L. Henderson, Jerry M. Soden, Charles F. Hawkins. 302-310
• Stuck Fault and Current Testing Comparison Using CMOS Chip TestThomas M. Storey, Wojciech Maly, John Andrews, Myron Miske. 311-318
• A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic AssembliesJohn McWha, Peter Kouklamanis. 319-326
• Fault Diagnosis using Functional Fault Models for VHDL descriptionsVijay Pitchumani, Pankaj Mayor, Nimish Radia. 327-337
• A Pragmatic Test Data Management SystemGordon F. Taylor, Steven M. Blumenau. 338-344
• Characterization and Control of PLCC and MQFP Lead Inspection SystemsScott A. Erjavic. 345-353
• Electromigration Effects in VLSI Due to Various Current TypesE. Weis, E. Kinsbron, M. Snyder, B. Vogel, N. Croitoru. 354-357
• The Effect of Different Test Sets on Quality Level Prediction: When is 80 better than 90 ?Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang. 358-364
• Design for Testability: Using Scanpath Techniques for Path-Delay Test and MeasurementBulent I. Dervisoglu, Gayvin E. Stong. 365-374
• Hierarchical Test Program Development for Scan Testable CircuitsJens Leenstra, Lambert Spaanenburg. 375-384
• Selectable Length Partial Scan: A Method to Reduce Vector LengthSean P. Morley, Ralph Marlett. 385-392
• On Multiple Path Propagating Tests for Path Delay FaultsAnkan K. Pramanick, Sudhakar M. Reddy. 393-402
• A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential CircuitsKwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer. 403-410
• An Accurate Bridging Fault Test Pattern GeneratorSteven D. Millman, James P. Garvey Sr.. 411-418
• An Intelligent Approach to Automatic Test EquipmentWilliam R. Simpson, John W. Sheppard. 419-425
• A Densely Integrated High Performance CMOS TesterGary J. Lesmeister. 426-429
• Arbitrary Waveform Generation with Absolute Duration ControlBryan J. Dinteman. 430-436
• Effective Implementation of Statistical Process Control in an Integrated Circuit Test EnvironmentSally Wilk. 437-445
• Statistical Product Monitoring: A Powerful Tool for Quality ImprovementBarbara Cole, Glen Herzog, Phung Ngo, Steven Hinkle, Peter Sherry. 446-453
• Don t Eliminate Incoming Test - Move ItD. L. Smoot, Babur Mustafa Pulat. 454-462
• Allocation and Assignment in High-Level Synthesis for Self-Testable Data PathsLaNae J. Avra. 463-472
• Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level CircuitsStephen Pateras, Janusz Rajski. 473-482
• Can Redundancy Enhance Testability?Andrzej Krasniewski. 483-491
• Test Pattern Generation for Realistic Bridge Faults in CMOS ICsF. Joel Ferguson, Tracy Larrabee. 492-499
• IC Defects-Based Testability AnalysisJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira. 500-509
• Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOSRosa Rodríguez-Montañés, J. A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio. 510-519
• Integrating CrossCheck Technology into the Raytheon Test EnvironmentStephen M. Lorusso, Paul N. Bompastore, Michael T. Fertsch. 520-529
• High-Density CMOS Multichip-Module Testing and DiagnosisRobert W. Bassett, Pamela S. Gillis, John J. Shushereba. 530-539
• Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy SchemeJ. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama. 540-547
• Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIMH.-D. Oberle, Peter Muhmenthaler. 548-555
• An Address Maskable Parallel Testing for Ultra High Density DRAMsYoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada. 556-563
• Fault Modeling for the Testing of Mixed Integrated CircuitsAnne Meixner, Wojciech Maly. 564-572
• Linear Error Modeling of Analog and Mixed-Signal DevicesGerard N. Stenbakken, T. Michael Souders. 573-581
• Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous ChecksumsAbhijit Chatterjee. 582-591
• Test Vector Generation for Linear Analog DevicesSheng-Jen Tsai. 592-597
• On Test Generation for Iddq Testing of Bridging Faults in CMOS CircuitsS. Wayne Bollinger, Scott F. Midkiff. 598-607
• A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor FaultsE. Vandris, Gerald E. Sobelman. 608-614
• High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation AlgorithmsChun-Hung Chen, Jacob A. Abraham. 615-622
• Fault Location with Current MonitoringRobert C. Aitken. 623-632
• Enhancing Board Functional Self-Test by Concurrent SamplingKenneth D. Wagner, Thomas W. Williams. 633-640
• Circuit Pack BIST from System to Factory - The MCERT ChipPartha Raghavachari. 641-648
• Achieving Board-Level BIST Using the Boundary-Scan MasterNajmi T. Jarwala, Chi W. Yau. 649-658
• A Case Study of Mixed Signal Fault Isolation: Knowledge Based vs. Decision Tree ProgrammingCharles W. Buenzli Jr., Robert Gonzalez. 659-664
• Fault Modeling and Testing of GaAs Static Random Access MemoriesSundarar Mohan, Pinaki Mazumder. 665-674
• An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive FaultsManoj Franklin, Kewal K. Saluja. 675-684
• Locating Bridging Faults in Memory ArraysA. J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp. 685-694
• Built-In Self-Diagnostic Read-Only-MemoriesPrawat Nagvajara, Mark G. Karpovsky. 695-703
• Two-Pattern Test Capabilities of Autonomous TPG CircuitsKiyoshi Furuya, Edward J. McCluskey. 704-711
• Defect Level Estimation of Random and Pseudorandom TestingWen-Ben Jone. 712-721
• At-Speed Test is not Necessarily an AC TestJacob Savir, Robert F. Berry. 722-728
• ARTEST: An Architectural Level Test Generator for Data Path Faults and Control FaultsJaushin Lee, Janak H. Patel. 729-738
• Hierarchical Test Generation Based on Delayed PropagationMargot Karam, Régis Leveugle, Gabriele Saucier. 739-747
• Test Propagation Through Modules and CircuitsBrian T. Murray, John P. Hayes. 748-757
• A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection CapabilityMarius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie. 758-767
• An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System BackplanesDilip K. Bhavsar. 768-776
• High Performance Pin Electronics Employing GaAs IC and Hybrid Circuit Packaging TechnologyBarry Baril, Dan Clayson, David McCracken, Stewart Taylor. 777-789
• Real-Time Data Comparison for GigaHertz Digital TestDavid C. Keezer. 790-797
• Delay Testing of Digital Circuits by Output Waveform AnalysisPiero Franco, Edward J. McCluskey. 798-807
• Fast Signature Computation for Linear CompactorsD. Lambidonis, André Ivanov, Vinod K. Agarwal. 808-817
• Refined Bounds on Signature Analysis Aliasing for Random TestingNirmal R. Saxena, Piero Franco, Edward J. McCluskey. 818-827
• Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error ModelMark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan. 828-839
• Test Application Timing: The Unexplored Issue in AC TestVijay S. Iyengar, Gopalakrishnan Vijayan. 840-847
• Hardware Acceleration Alone Will Not Make Fault Grading ULSI a RealityGopi Ganapathy, Jacob A. Abraham. 848-857
• Looking for Functional Fault EquivalenceAntonio Lioy. 858-863
• Using Boundary Scan Description Language in DesignDick Chiles, John DeJaco. 865-868
• An IEEE 1149.1 Based Logic/Signature Analyzer in a ChipLee Whetsel. 869-878
• Implementing 1149.1 on CMOS MicroprocessorsW. C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns. 879-886
• Gate-Delay-Fault Testability Properties of Multiplexor-Based NetworksPranav Ashar, Srinivas Devadas, Kurt Keutzer. 887-896
• Delay Testing Quality in Timing-Optimized DesignsEun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer. 897-905
• Logic Partitioning and Resynthesis for TestabilityKaushik De, Prithviraj Banerjee. 906-915
• Low Overhead Built-In Testable Error Detection and Correction with Excellent Fault CoverageMehdi Katoozi, Arnold Nordsiek. 916-925
• Concurrent Error Detection for Restricted Fault Sets in Sequential Circuits and Microprogrammed Control Units Using Convolutional CodesLawrence P. Holmquist, Larry L. Kinney. 926-935
• Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC MultiprocessorsX. Delord, Gabriele Saucier. 936-945
• An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault PropagationHyung Ki Lee, Dong Sam Ha. 946-955
• Multiple-Fault Simulation and Coverage of Deterministic Single-Fault Test SetsKen Kubiak, W. Kent Fuchs. 956-962
• Two-Stage Fault LocationPaul G. Ryan, Shishpal Rawat, W. Kent Fuchs. 963-968
• A Picosecond Accuracy Timing Error Compensation Technique in TDR MeasurementTaiichi Otsuji. 969-975
• Maximizing and Maintaining AC Test Accuracy in the Manufacturing EnvironmentRaymond J. Bulaga, Edward F. Westermann. 976-985
• DSP Calibration for Accurate Time Waveform ReconstructionEric Rosenfeld, Bradford Sumner. 986-993
• Integrating Emulation Techniques into General Purpose ATER. Wade Williams. 994-1003
• The enVision:::TM::: Timing ResolverDon Organ. 1004-1008
• Distributed Layout Verification Using Sequential Software and Standard HardwareYehuda Shiran. 1009-1015
• Parity Bit Calculation and Test Signal Compaction for BIST ApplicationsSungju Park, Sheldon B. Akers. 1016-1023
• On the Testable Design of Bilateral Bit-Level Systolic ArraysSubir Bandyopadhyay, Bhargab B. Bhattacharya. 1024-1033
• An Organized Firmware Verification Environment for the Programmable Image DSPYutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki. 1034-1041
• A Computer Architecture for High Pin Count TestersChristopher J. Hannaford. 1042-1048
• A 20 Bit Waveform Source for a Mixed Signal Automatic Test SystemDaniel A. Rosenthal. 1049-1054
• Advanced Mixed Signal Testing by DSP Localized TesterKoji Karube, Yoshiyuki Bessho, Tokuo Takakura, Keita Gunji. 1055-1060
• Programming for Parallel Pattern GeneratorsM. Kanzaki, Masahiro Ishida. 1061-1068
• High Frequency Wafer Probing and Power Supply Resonance EffectsS. P. Athan, David C. Keezer, J. McKinley. 1069-1078
• A Flexible Approach to Test Program Cross CompilersMichael A. Perugini. 1079-1086
• Industry Graphic Standards and ATE Windowing SoftwareArthur E. Downey. 1087-1095
• A Workstation Environment for Boundary Scan Interconnect TestingTimothy J. Moore. 1096-1103
• Languages to Support Boundary-Scan TestColin Maunder. 1104
• Representing Boundary Scan Tests with the EDIF Test ViewCarol Pyron. 1105
• Software Testing, the State of the PracticeTed W. Gary. 1106
• Software Testing - The State of the PracticeEdward F. Miller. 1107
• Unit Testing Versus Integration TestingA. Jefferson Offutt. 1108-1109
• Software TestingPaul D. Roddy. 1110
• For Test Automation, Silicon is FreeTushar Gheewala. 1111
• Distractions in Design for Testability and Built-Is Self-TestCharles E. Stroud. 1112
• Military Burn-In Requirements - One PerspectiveDaniel J. Burns. 1113
• Is Burn-In Burned Out?Noel E. Donlin. 1114-1115
• Is Burn-In Burned Out?Charles C. Packard. 1116
• Can Undergraduate Test Engineering Education Be Faster, Better, Sooner? Richard Absher. 1117
• EE Curriculum - Continuous Process Improvement?Charles F. Hawkins, Richard H. Williams. 1118
• Improving the Quality of Test EducationWojciech Maly. 1119
• The Interaction of Test and QualityPeter C. Maxwell. 1120
• Quality in Test Education?Kenneth Rose. 1121