Ankan K. Pramanick - researchr alias

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Viewing Publication 1 - 15 from 15

2005

Parallel, multi-DUT testing in an open architecture test systemToshiaki Adachi, Ankan K. Pramanick, Mark Elston. itc 2005: 9 [doi]

2004

Software development for an open architecture test systemBruce R. Parnas, Ankan K. Pramanick, Mark Elston, Toshiaki Adachi. ets 2004: 38-43 [doi]

Test Programming Environment in a Modular, Open Architecture Test SystemAnkan K. Pramanick, Ramachandran Krishnaswamy, Mark Elston, Toshiaki Adachi, Harsanjeet Singh, Bruce R. Parnas. itc 2003: 413-422 [doi]

1997

On the fault coverage of gate delay fault detecting testsAnkan K. Pramanick, Sudhakar M. Reddy. tcad, 16(1):78-94, 1997. [doi]

1995

Parallel Delay Fault Coverage and Test Quality EvaluationIra Pramanick, Ankan K. Pramanick. itc 1995: 113-122

Efficient multiple path propagating tests for delay faultsAnkan K. Pramanick, Sudhakar M. Reddy. et, 7(3):157-172, 1995. [doi]

1994

Distributed Solutions to the Delay Fault Test Quality Evaluation ProblemIra Pramanick, Ankan K. Pramanick. hpdc 1994: 177-185

1993

Testability preserving Boolean transforms for logic synthesisSandip Kundu, Ankan K. Pramanick. vts 1993: 131-138 [doi]

On Unified Delay Fault TestingAnkan K. Pramanick, Sudhakar M. Reddy. vlsid 1993: 265-268

Design of Scan-Based Path-Delay-Testable Sequential CircuitsAnkan K. Pramanick, Sandip Kundu. itc 1993: 962-971

1991

On Multiple Path Propagating Tests for Path Delay FaultsAnkan K. Pramanick, Sudhakar M. Reddy. itc 1991: 393-402

1990

On the fault coverage of delay fault detecting testsAnkan K. Pramanick, Sudhakar M. Reddy. eurodac 1990: 334-338 [doi]

On the design of path delay fault testable combinational circuitsAnkan K. Pramanick, Sudhakar M. Reddy. ftcs 1990: 374-381 [doi]

1989

On the computation of the ranges of detected delay fault sizesAnkan K. Pramanick, Sudhakar M. Reddy. iccad 1989: 126-129 [doi]

1988

On the Detection of Delay FaultsAnkan K. Pramanick, Sudhakar M. Reddy. itc 1988: 845-856

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