Table of Contents

• A distributed BIST control scheme for complex VLSI devicesYervant Zorian. 4-9 [doi]
• A new built-in self-test method based on prestored testingGeetani Edirisooriya, Samantha Edirisooriya, John P. Robinson. 10-16 [doi]
• Minimal hardware multiple signature analysis for BISTYuejian Wu, André Ivanov. 17-20 [doi]
• Analysis of redundant structures in combinational circuitsEugeni Isern, Joan Figueras. 21-23 [doi]
• DDQ tests for bridging faults in combinational circuitsSreejit Chakravarty, Paul J. Thadikaran. 25-32 [doi]
• Quiescent current estimation based on quality requirementsFabian Luis Vargas, Michael Nicolaidis, B. Hamdi. 33-39 [doi]
• An IEEE 1149.1 based voltmeter/oscilloscope in a chipLee Whetsel. 40-46 [doi]
• Input and output encoding techniques for on-line error detection in combinational logic circuitsFadi Y. Busaba, Parag K. Lala. 48-54 [doi]
• Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processingGuoning Liao. 55-61 [doi]
• On the check base selection problem for fast addersUwe Sparmann. 62-65 [doi]
• Finitely self-checking circuits and their application on current sensorsMichael Nicolaidis. 66-69 [doi]
• Parallelization methods for circuit partitioning based parallel automatic test pattern generationRobert H. Klenke, Ronald D. Williams, James H. Aylor. 71-78 [doi]
• CCSTG: an efficient test pattern generator for sequential circuitsKyuchull Kim, Kewal K. Saluja. 79-84 [doi]
• Explorations of sequential ATPG using Boolean satisfiabilityHaluk Konuk, Tracy Larrabee. 85-90 [doi]
• Carafe: an inductive fault analysis tool for CMOS VLSI circuitsAlvin Jee, F. Joel Ferguson. 92-98 [doi]
• The effect of defect clustering on test transparency and defect levelsAdit D. Singh, C. Mani Krishna. 99-105 [doi]
• DDQ testingSamir B. Naik, Wojciech P. Maly. 106-108 [doi]
• Fault injection scan design for enhanced VLSI design verificationSavio N. Chau. 109-111 [doi]
• Classification of bridging faults in CMOS circuits: experimental results and implications for testScott F. Midkiff, S. Wayne Bollinger. 112-115 [doi]
• On CMOS bridge fault modeling and test pattern evaluationChennian Di, Jochen A. G. Jess. 116-119 [doi]
• Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probingFriedrich Taenzler, Thomas Novak 0003, Erich Kubalek. 120-122 [doi]
• Generation of testable designs from behavioral descriptions using high level synthesis toolsK. K. Varma, P. Vishakantaiah, J. A. Abraham. 124-130 [doi]
• Testability preserving Boolean transforms for logic synthesisSandip Kundu, Ankan K. Pramanick. 131-138 [doi]
• Testability analysis based on structural and behavioral informationJaushin Lee, Janak H. Patel. 139-146 [doi]
• On the design for testability of sequential circuitsXiao Sun 0002, Fabrizio Lombardi. 147-150 [doi]
• Revisiting shift register realization for ease of test generation and testingShunichi Toida. 151-153 [doi]
• Controllability and observability measures for functional-level testability evaluationMohamed Jamoussi, Bozena Kaminska. 154-157 [doi]
• Defect-tolerant cache memory designDan Lamet, James F. Frenzel. 159-163 [doi]
• Design SRAMs for burn-inWilliam R. Reohr, Yuen H. Chan, Donald W. Plass, Antonio Pelella, Philip T. Wu. 164-170 [doi]
• ECC design of a custom DRAM storage unitJean-Luc Peter. 171-173 [doi]
• Concurrent error correction in iterative circuits by recomputing with partitioning and votingHussain Al-Asaad, Edward C. Czeck. 174-177 [doi]
• Testability of one dimensional ILAs under multiple faultsMurali M. R. Gala, Karan L. Watson, Don E. Ross. 178-181 [doi]
• Degrading fault model for WSI interconnection linesHussam Y. Abujbara, Sami A. Al-Arian. 182-185 [doi]
• Worst-case analysis for pseudorandom testingRadu Marculescu. 187-193 [doi]
• Signal probability calculations using partial functional manipulationRavishankar Kodavarti, Don E. Ross. 194-200 [doi]
• LFSR based deterministic hardware for at-speed BISTBeena Vasudevan, Don E. Ross, Murali M. R. Gala, Karan L. Watson. 201-207 [doi]
• LFSROM an algorithm for automatic design synthesis of hardware test pattern generatorChristian Dufaza, Cyril Chevalier, Lew Fock Chong Lew Yan Voon. 208-214 [doi]
• Improvement of analog circuit fault detectability using fault detection observersWolfgang Vermeiren, Wolfgang Straube, Günter Elst. 218-224 [doi]
• Hard faults diagnosis in analog circuits using sensitivity analysisYunsheng Lu, Ramaswami Dandapani. 225-229 [doi]
• Automatic synthesis of DUT board circuits for testing of mixed signal ICsWilliam H. Kao, Jean Qincui Xia. 230-236 [doi]
• A neural inverse function for automatic test pattern generation using strictly digital neural networksMasatoshi Arai, Tohru Nakagawa, Hajime Kitagawa. 238-243 [doi]
• Incremental test pattern generationSang-Hoon Song, Larry L. Kinney. 244-250 [doi]
• Combinational circuit ATPG using binary decision diagramsSanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer. 251-258 [doi]
• Aliasing-free error detection (ALFRED)Krishnendu Chakrabarty, John P. Hayes. 260-266 [doi]
• On the maximum value of aliasing probabilities for single input signature registersShou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki. 267-274 [doi]
• Time and space correlated errors in signature analysisGeetani Edirisooriya, Samantha Edirisooriya, John P. Robinson. 275-281 [doi]
• Aliasing computation using fault simulation with fault droppingIrith Pomeranz, Sudhakar M. Reddy. 282-288 [doi]
• Physical design for testability for bridges in CMOS circuitsF. Joel Ferguson. 290-295 [doi]
• Testable design for BiCMOS stuck-open fault detectionSankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. 296-302 [doi]
• On diagnosis of faults in a scan-chainSandip Kundu. 303-308 [doi]
• Impact of high level functional constraints on testabilityJaushin Lee, Vivek Chickermane, Janak H. Patel. 309-312 [doi]
• Partial scan testing with single clock controlVishwani D. Agrawal, Tapan J. Chakraborty. 313-315 [doi]
• Estimation of reject ratio in testing of combinatorial circuitsDinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly. 319-325 [doi]
• Functional verification and simulation of FSM networksZafar Hasan, Maciej J. Ciesielski. 326-332 [doi]
• A structured design for test methodologyKumar Venkat. 333-336 [doi]
• A model for testing reliable VLSI routing architecturesConstantine Stivaros. 337-339 [doi]
• On parallel switch level fault simulationChristopher A. Ryan, Joseph G. Tront. 341-347 [doi]
• Evaluation of test generation algorithmsYinghua Min, Zhongcheng Li. 348-350 [doi]
• Simulation of non-classical faults on the gate level-fault modelingJürgen Alt, Udo Mahlstedt. 351-354 [doi]
• Sensitivity analysis of a radiation immune CMOS logic family under defect conditionsErik H. Ingermann, James F. Frenzel. 355-357 [doi]
• Pattern generator card, emulation, and debugStephen M. Dunn, D. G. Balazich, Lawrence K. Lange, Charlotte C. Montillo. 358-360 [doi]