Tapan J. Chakraborty - researchr alias

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Viewing Publication 1 - 27 from 27

2013

Functional Fmax test-time reduction using novel DFTs for circuit initializationUjjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor. iccd 2013: 1-6 [doi]

2010

A Common Language Framework for Next-Generation Embedded TestingMichele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook. dt, 27(5):36-49, 2010. [doi]

2008

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational CircuitsAditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty. vlsid 2008: 39-44 [doi]

A New Language Approach for IJTAGMichele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook. itc 2008: 1-10 [doi]

2007

2005

Efficient Test Architecture based on Boundary Scan for Comprehensive System TestTapan J. Chakraborty. ats 2005: 464-465 [doi]

2002

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan ArchitecturTapan J. Chakraborty, Chen-Huan Chiang. itc 2002: 923-929 [doi]

2000

Improving path delay testability of sequential circuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. tvlsi, 8(6):736-741, 2000. [doi]

Path delay fault simulation of sequential circuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. tvlsi, 8(2):223-228, 2000. [doi]

1999

Built in self test: a complete test solution for telecommunication systemsNilanjan Mukherjee 0001, Tapan J. Chakraborty, Ramesh Karri. cm, 37(6):72-78, 1999. [doi]

1998

A BIST scheme for the detection of path-delay faultsNilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik. itc 1998: 422 [doi]

1997

Effective Path Selection for Delay Fault Testing of Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal. itc 1997: 998-1003

On variable clock methods for path delay testing of sequential circuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. tcad, 16(11):1237-1249, 1997. [doi]

1996

Design for high-speed testability of stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. vlsid 1996: 53-56 [doi]

1995

High-Performance Circuit Testing with Slow-Speed TestersVishwani D. Agrawal, Tapan J. Chakraborty. itc 1995: 302-310

Simulation of at-speed tests for stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. vts 1995: 216-220 [doi]

Robust testing for stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. vlsid 1995: 42-46 [doi]

1994

Delay independent initialization of sequential circuitsTapan J. Chakraborty, Vishwani D. Agrawal. glvlsi 1994: 228-230 [doi]

1993

Partial scan testing with single clock controlVishwani D. Agrawal, Tapan J. Chakraborty. vts 1993: 313-315 [doi]

Design for Testability for Path Delay faults in Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. dac 1993: 453-457 [doi]

1992

Delay Fault Models and Test Generation for Random Logic Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. dac 1992: 165-172 [doi]

1991

Enhanced Controllability for ::::I::DDQ:::::: Test Sets Using Partial ScanTapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin. dac 1991: 278-281 [doi]

On behavior fault modeling for digital designsSumit Ghosh, Tapan J. Chakraborty. et, 2(2):135-151, 1991. [doi]

1989

Gentest: An Automatic Test-Generation System for Sequential CircuitsWu-Tung Cheng, Tapan J. Chakraborty. Computer, 22(4):43-49, 1989.

1988

On Behavior Fault Modeling for Combinational Digital DesignsTapan J. Chakraborty, Sumit Ghosh. itc 1988: 593-600

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