Sudipta Bhawmik - researchr alias

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Viewing Publication 1 - 30 from 30

2015

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICsRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. tcad, 34(1):136-149, 2015. [doi]

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D ICRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. todaes, 20(4):58, 2015. [doi]

2014

At-speed interconnect testing and test-path optimization for 2.5D ICsRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. vts 2014: 1-6 [doi]

Built-in self-test for interposer-based 2.5D ICsRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. iccd 2014: 181-188 [doi]

2013

Using 3D-COSTAR for 2.5D test cost optimizationMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik. 3dic 2013: 1-8 [doi]

Impact of mid-bond testing in 3D stacked ICsMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik. dft 2013: 178-183 [doi]

2003

The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT DataMichael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod. itc 2003: 998-1007 [doi]

2002

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) SwitchSubhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik. et, 18(4-5):475-485, 2002. [doi]

Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) SwitchSubhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik. vlsid 2002: 598-603 [doi]

2001

ntroduction to SystemCSudipta Bhawmik. vlsid 2001: 7-8

2000

A BIST scheme for RTL circuits based on symbolic testabilityanalysisIndradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik. tcad, 19(1):111-128, 2000. [doi]

Core Based ASIC DesignFrank P. Higgins, Sudipta Bhawmik. vlsid 2000: 10

On improving test quality of scan-based BISTHuan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik. tcad, 19(8):928-938, 2000. [doi]

1999

Improving the Test Quality for Scan-Based BIST Using a General Test Application SchemeHuan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik. dac 1999: 748-753 [doi]

POWERTEST: A Tool for Energy Conscious Weighted Random Pattern TestingXiaodong Zhang, Kaushik Roy, Sudipta Bhawmik. vlsid 1999: 416-422

1998

1997

A Practical Method for Selecting Partial Scan Flip-flops for Large CircuitsSudipta Bhawmik, Indradeep Ghosh. vlsid 1997: 284-288 [doi]

A Hybrid Algorithm for Test Point Selection for Scan-Based BISTHuan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik. dac 1997: 478-483 [doi]

1995

Integration of partial scan and built-in self-testChih-Jen Lin, Yervant Zorian, Sudipta Bhawmik. et, 7(1-2):125-137, 1995. [doi]

1993

PSBIST: A Partial-Scan Based Built-In Self-Test SchemeChih-Jen Lin, Yervant Zorian, Sudipta Bhawmik. itc 1993: 507-516

1991

Enhanced Controllability for ::::I::DDQ:::::: Test Sets Using Partial ScanTapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin. dac 1991: 278-281 [doi]

1989

1988

DFTEXPERT: An Expert System for Design of Testable VLSI CircuitsSudipta Bhawmik, P. Pal Chaudhuri. ieaaie 1988: 388-396 [doi]

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