Abstract is missing.
- An Improved Algorithm for Minimum-Area RetimingNaresh Maheshwari, Sachin S. Sapatnekar. 2-7 [doi]
- Efficient Latch Optimization Using Exclusive SetsEllen Sentovich, Horia Toma, Gérard Berry. 8-11 [doi]
- Sequence Compaction for Probabilistic Analysis of Finite-State MachinesDiana Marculescu, Radu Marculescu, Massoud Pedram. 12-15 [doi]
- Synthesis of Speed-Independent Circuits from STG-Unfolding SegmentAlexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella. 16-21 [doi]
- Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency ControlLuca Benini, Enrico Macii, Massimo Poncino. 22-27 [doi]
- Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect NetworksIbrahim M. Elfadel, David D. Ling. 28-33 [doi]
- Preservation of Passivity During RLC Network Reduction via Split Congruence TransformationsKevin J. Kerns, Andrew T. Yang. 34-39 [doi]
- Lumped Interconnect Models Via Gaussian QuadratureKeith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert. 40-45 [doi]
- Calculating Worst-Case Gate Delays Due to Dominant Capacitance CouplingFlorentin Dartu, Lawrence T. Pileggi. 46-51 [doi]
- Schedule Validation for Embedded Reactive Real-Time SystemsFelice Balarin, Alberto L. Sangiovanni-Vincentelli. 52-57 [doi]
- Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous MultiprocessorsYosef Gavriel Tirat-Gefen, Diógenes Cecilio da Silva Jr., Alice C. Parker. 58-63 [doi]
- Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA TargetsMarleen Adé, Rudy Lauwereins, J. A. Peperstraete. 64-69 [doi]
- An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design EnvironmentStan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta. 70-75 [doi]
- Tools and Methodologies for Low Power DesignJerry Frenkil. 76-81 [doi]
- A C-Based RTL Design Verification Methodology for Complex MicroprocessorJoon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung. 83-88 [doi]
- Efficient Testing of Clock Regenerator Circuits in Scan DesignsRajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh. 95-100 [doi]
- A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation ApplicationsWen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen. 101-106 [doi]
- A Graph-Based Synthesis Algorithm for AND/XOR NetworksYibin Ye, Kaushik Roy. 107-112 [doi]
- Optimizing Designs Containing Black BoxesTai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal. 113-116 [doi]
- Solving Covering Problems Using LPR-Based Lower BoundsStan Y. Liao, Srinivas Devadas. 117-120 [doi]
- Exact Coloring of Real-Life Graphs is EasyOlivier Coudert. 121-126 [doi]
- Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect ModelingE. Aykut Dengi, Ronald A. Rohrer. 127-132 [doi]
- Bounds for BEM Capacitance ExtractionMichael W. Beattie, Lawrence T. Pileggi. 133-136 [doi]
- SPIE: Sparse Partial Inductance ExtractionZhijiang He, Mustafa Celik, Lawrence T. Pileggi. 137-140 [doi]
- A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMsSharad Kapur, Jinsong Zhao. 141-146 [doi]
- Static Timing Analysis of Embedded SoftwareSharad Malik, Margaret Martonosi, Yau-Tsun Steven Li. 147-152 [doi]
- A Task-Level Hierarchical Memory Model for System Synthesis of MultiprocessorsYanbing Li, Wayne Wolf. 153-156 [doi]
- Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded SystemsRajeshkumar S. Sambandam, Xiaobo Hu. 157-160 [doi]
- Formal Verification of a Superscalar Execution UnitKyle L. Nelson, Alok Jain, Randal E. Bryant. 161-166 [doi]
- Formal Verification of Content Addressable Memories Using Symbolic Trajectory EvaluationManish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir. 167-172 [doi]
- Formal Verification of FIRE: A Case StudyJae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley. 173-177 [doi]
- Interface-Based DesignJames A. Rowson, Alberto L. Sangiovanni-Vincentelli. 178-183 [doi]
- An Integrated Design Environment for Performance and Dependability AnalysisRobert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh. 184-189 [doi]
- A Dynamic Design Estimation and Exploration EnvironmentOle Bentz, Jan M. Rabaey, David Lidsky. 190-195 [doi]
- Remembrance of Things Past: Locality and Memory in BDDsSrilatha Manne, Dirk Grunwald, Fabio Somenzi. 196-201 [doi]
- Linear Sifting of Decision DiagramsChristoph Meinel, Fabio Somenzi, Thorsten Theobald. 202-207 [doi]
- Safe BDD Minimization Using Don t CaresYoupyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan. 208-213 [doi]
- Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater InsertionJohn Lillis, Chung-Kuan Cheng. 214-219 [doi]
- Exact Required Time Analysis via False Path DetectionYuji Kukimoto, Robert K. Brayton. 220-225 [doi]
- Symbolic Timing Verification of Timing Diagrams using Presburger FormulasTod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu. 226-231 [doi]
- Code Generation for Core ProcessorsPeter Marwedel. 232-237 [doi]
- Interface Timing Verification Drives System DesignAjay J. Daga, Peter Suaris. 240-245 [doi]
- Memory-CPU Size Optimization for Embedded System DesignsBarry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura. 246-251 [doi]
- Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case StudyMiodrag Potkonjak, Kyosun Kim, Ramesh Karri. 252-257 [doi]
- Formal Verification in a Commercial SettingRobert P. Kurshan. 258-262 [doi]
- Equivalence Checking Using Cuts and HeapsAndreas Kuehlmann, Florian Krohm. 263-268 [doi]
- Efficient Methods for Simulating Highly Nonlinear Multi-Rate CircuitsJaijeet S. Roychowdhury. 269-274 [doi]
- Rapid Frequency-Domain Analog Fault Simulation Under Parameter TolerancesMichael W. Tian, C.-J. Richard Shi. 275-280 [doi]
- SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor SystemsSalvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas. 281-286 [doi]
- Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP ArchitecturesAshok Sudarsanam, Stan Y. Liao, Srinivas Devadas. 287-292 [doi]
- System Level Fixed-Point Design Based on an Interpolative ApproachMarkus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr. 293-298 [doi]
- ISDL: An Instruction Set Description Language for RetargetabilityGeorge Hadjiyiannis, Silvina Hanono, Srinivas Devadas. 299-302 [doi]
- Generation of Software Tools from Processor Descriptions for Hardware/Software CodesignMark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar. 303-306 [doi]
- Education for the Deep Submicron Age: Business as Usual?Hugo De Man. 307-312 [doi]
- InfoPad - An Experiment in System Level Design and IntegrationRobert W. Brodersen. 313-314 [doi]
- Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design MethodologiesAsim Smailagic, Daniel P. Siewiorek, Richard Martin, John Stivoric. 315-320 [doi]
- CAD at the Design-Manufacturing InterfaceHans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz. 321-326 [doi]
- CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell LibrariesMohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones. 327-332 [doi]
- Developing a Concurrent Methodology for Standard-Cell Library GenerationDonald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson. 333-336 [doi]
- A Fast And Accurate Technique To Optimize Characterization Tables For Logic SynthesisJohn F. Croix, D. F. Wong. 337-340 [doi]
- Limited Exception Modeling and Its Use in Presynthesis OptimizationsJian Li, Rajesh K. Gupta. 341-346 [doi]
- Potential-Driven Statistical Ordering of TransformationsInki Hong, Darko Kirovski, Miodrag Potkonjak. 347-352 [doi]
- Synthesis of Application Specific Programmable ProcessorsKyosun Kim, Ramesh Karri, Miodrag Potkonjak. 353-358 [doi]
- Symbolic Evaluation of Performance Models for Tradeoff VisualizationJeffrey Walrath, Ranga Vemuri. 359-364 [doi]
- Power Macromodeling for High Level Power EstimationSubodh Gupta, Farid N. Najm. 365-370 [doi]
- Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI CirucitsChih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram. 371-376 [doi]
- Statistical Estimation of Average Power Dissipation in Sequential CircuitsLi-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang. 377-382 [doi]
- Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS CircuitsAngela Krstic, Kwang-Ting Cheng. 383-388 [doi]
- Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off AnalysisClaudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli. 389-394 [doi]
- Dynamic Communication Models in Embedded System Co-SimulationKen Hines, Gaetano Borriello. 395-400 [doi]
- Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic NetworksPankaj Pant, Vivek De, Abhijit Chatterjee. 403-408 [doi]
- Transistor Sizing Issues and Tool For Multi-Threshold CMOS TechnologyJames Kao, Anantha Chandrakasan, Dimitri Antoniadis. 409-414 [doi]
- Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCTThucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan. 415-420 [doi]
- A Power Estimation Framework for Designing Low Power Portable Video ApplicationsChi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram. 421-424 [doi]
- An Investigation of Power Delay Trade-Offs on PowerPC CircuitsQi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly. 425-428 [doi]
- Power Management Techniques for Control-Flow Intensive DesignsAnand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi. 429-434 [doi]
- Low Energy Memory and Register Allocation Using Network FlowCatherine H. Gebotys. 435-440 [doi]
- Power-conscious High Level Synthesis Using Loop FoldingDaehong Kim, Kiyoung Choi. 441-445 [doi]
- The Future of Custom Cell Generation in Physical SynthesisMartin Lefebvre, David Marple, Carl Sechen. 446-451 [doi]
- CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS CellsAvaneendra Gupta, John P. Hayes. 452-455 [doi]
- An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout DesignJaewon Kim, Sung-Mo Kang. 456-459 [doi]
- A Test Synthesis Approach to Reducing BALLAST DFT OverheadDouglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng. 466-471 [doi]
- STARBIST: Scan Autocorrelated Random Pattern GenerationKun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska. 472-477 [doi]
- A Hybrid Algorithm for Test Point Selection for Scan-Based BISTHuan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik. 478-483 [doi]
- Design and Synthesis of Array Structured Telecommunication Processing ApplicationsWolfgang Meyer, Andrew Seawright, Fumiya Tada. 486-491 [doi]
- A Parallel/Serial Trade-Off Methodology for Look-Up Table Based DecodersClaus Schneider. 498-503 [doi]
- High-Level Power Modeling, Estimation, and OptimizationEnrico Macii, Massoud Pedram, Fabio Somenzi. 504-511 [doi]
- A Network Flow Approach for Hierarchical Tree PartitioningMing-Ter Kuo, Chung-Kuan Cheng. 512-517 [doi]
- Multi-Way FPGA Partitioning by Fully Exploiting Design HierarchyWen-Jong Fang, Allen C.-H. Wu. 518-521 [doi]
- A Hierarchy-Driven FPGA Partitioning MethodHelena Krupnova, Ali Abbara, Gabriele Saucier. 522-525 [doi]
- Multilevel Hypergraph Partitioning: Application in VLSI DomainGeorge Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar. 526-529 [doi]
- Multilevel Circuit PartitioningCharles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng. 530-533 [doi]
- Hierarchical Test Generation and Design for Testability of ASPPs and ASIPsIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha. 534-539 [doi]
- Frequency-Domain Compatibility in Digital Filter BISTLaurence Goodby, Alex Orailoglu. 540-545 [doi]
- A Scheme for Integrated Controller-Datapath Fault TestingMehrdad Nourani, Joan Carletta, Christos A. Papachristou. 546-551 [doi]
- Executable Workflows: A Paradigm for Collaborative Design on the InternetHemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski. 553-558 [doi]
- Modeling Design Tasks and Tools: The Link Between Product and Flow ModelBernd Schürmann, Joachim Altmeyer. 564-569 [doi]
- Hierarchical Sequence Compaction for Power EstimationRadu Marculescu, Diana Marculescu, Massoud Pedram. 570-575 [doi]
- Profile-Driven Program Synthesis for Evaluation of System Power DissipationCheng-Ta Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar. 576-581 [doi]
- Analytical Estimation of Transition Activity From Word-Level Signal StatisticsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. 582-587 [doi]
- Wire Segmenting for Improved Buffer InsertionCharles J. Alpert, Anirudh Devgan. 588-593 [doi]
- More Practical Bounded-Skew Clock RoutingAndrew B. Kahng, Chung-Wen Albert Tsao. 594-599 [doi]
- An Efficient Approach to Multi-Layer Layer Assignment with Application to Via MinimizationChin-Chih Chang, Jason Cong. 600-603 [doi]
- Optimal Wire-Sizing Function with Fringing Capacitance ConsiderationChung-Ping Chen, D. F. Wong. 604-607 [doi]
- Fault Simulation under the Multiple Observation Time Approach using Backward ImplicationsIrith Pomeranz, Sudhakar M. Reddy. 608-613 [doi]
- ATPG for Heat Dissipation Minimization During Scan TestingSeongmoon Wang, Sandeep K. Gupta. 614-619 [doi]
- Automatic Generation of Synchronous Test Patterns for Asynchronous CircuitsOriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor. 620-625 [doi]
- Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction MethodologyJason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen. 627-632 [doi]
- Accurate and Efficient Macromodel of Submicron Digital Standard CellsCristiano Forzan, Bruno Franzini, Carlo Guardiani. 633-637 [doi]
- Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip DesignHoward H. Chen, David D. Ling. 638-643 [doi]
- FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential CircuitsJason Cong, Chang Wu. 644-649 [doi]
- Technology-Dependent Transformations for Low-Power SynthesisRajendran Panda, Farid N. Najm. 650-655 [doi]
- Low Power FPGA Design - A Re-engineering ApproachChau-Shen Chen, TingTing Hwang, C. L. Liu. 656-661 [doi]
- Post-Layout Logic Restructuring for Performance OptimizationYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska. 662-665 [doi]
- Layout Driven Re-synthesis for Low Power Consumption LSIsMasako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi. 666-669 [doi]
- Overview of Microelectromechanical Systems and Design ProcessesWilliam C. Tang. 670-673 [doi]
- CAD and Foundries for MicrosystemsJean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, András Poppe, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner. 674-679 [doi]
- Structured Design of Microelectromechanical SystemsTamal Mukherjee, Gary K. Fedder. 680-685 [doi]
- Algorithms for Coupled Domain MEMS SimulationNarayan R. Aluru, James White. 686-690 [doi]
- A Hardware/Software Partitioner Using a Dynamically Determined GranularityJörg Henkel, Rolf Ernst. 691-696 [doi]
- System-Level Synthesis of Low-Power Hard Real-Time SystemsDarko Kirovski, Miodrag Potkonjak. 697-702 [doi]
- COSYN: Hardware-Software Co-Synthesis of Embedded SystemsBharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha. 703-708 [doi]
- Data-Flow Assisted Behavioral Partitioning for Embedded SystemsSamir Agrawal, Rajesh K. Gupta. 709-712 [doi]
- Hardware/Software Partitioning and PipeliningSmita Bakshi, Daniel Gajski. 713-716 [doi]
- Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large CircuitsGianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer. 728-733 [doi]
- An Efficient Assertion Checker for Combinational PropertiesGagan Hasteer, Anmol Mathur, Prithviraj Banerjee. 734-739 [doi]
- Toward Formalizing a Validation Methodology Using Simulation CoverageAarti Gupta, Sharad Malik, Pranav Ashar. 740-745 [doi]
- Algorithms for Large-Scale Flat PlacementJens Vygen. 746-751 [doi]
- Quadratic Placement RevisitedCharles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan. 752-757 [doi]
- Unification of Budgeting and PlacementMajid Sarrafzadeh, David A. Knol, Gustavo E. Téllez. 758-761 [doi]
- Cluster Refinement for Block PlacementJin Xu, Pei-Ning Guo, Chung-Kuan Cheng. 762-765 [doi]
- Computer-Aided Design of Free-Space Opto-Electronic SystemsSteven P. Levitan, Philippe J. Marchand, Timothy P. Kurzweg, M. A. Rempel, Donald M. Chiarulli, C. Fan, F. B. McCormick. 768-773 [doi]
- Hardware/Software Co-Simulation in a VHDL-Based Test Bench ApproachMatthias Bauer, Wolfgang Ecker. 774-779 [doi]
- Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio ProcessorClifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher. 780-785 [doi]