Rajat Aggarwal - researchr alias

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Viewing Publication 1 - 15 from 15

2017

Clock-Aware FPGA Placement ContestStephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal. ispd 2017: 159-164 [doi]

2016

2015

Online handwriting recognition using depth sensorsRajat Aggarwal, Sirnam Swetha, Anoop M. Namboodiri, Jayanthi Sivaswamy, C. V. Jawahar. icdar 2015: 1061-1065 [doi]

2014

FPGA place & route challengesRajat Aggarwal. ispd 2014: 45-46 [doi]

2009

Solving modern mixed-size placement instancesJarrod A. Roy, Aaron N. Ng, Rajat Aggarwal, Venky Ramachandran, Igor L. Markov. integration, 42(2):262-275, 2009. [doi]

2008

Architecture-specific packing for virtex-5 FPGAsTaneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal. fpga 2008: 5-13 [doi]

2006

A Novel Earthquake Mitigation Information expert System: EMISPanneerselvam Kolandaivel, Rajat Aggarwal. ccece 2006: 337-340 [doi]

Solving hard instances of floorplacementAaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran. ispd 2006: 170-177 [doi]

1999

Multilevel hypergraph partitioning: applications in VLSI domainGeorge Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar. tvlsi, 7(1):69-79, 1999. [doi]

1997

Speeding up technology-independent timing optimization by network partitioningRajat Aggarwal, Rajeev Murgai, Masahiro Fujita. iccad 1997: 83-90 [doi]

Multilevel Hypergraph Partitioning: Application in VLSI DomainGeorge Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar. dac 1997: 526-529 [doi]

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