Abstract is missing.
- Commercial CAD: challenges and opportunitiesTed Vucurevich. 1 [doi]
- Robust extraction of spatial correlationJinjun Xiong, Vladimir Zolotov, Lei He. 2-9 [doi]
- Timing analysis in presence of supply voltage and temperature variationsB. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine. 10-16 [doi]
- Probabilistic evaluation of solutions in variability-driven optimizationAzadeh Davoodi, Ankur Srivastava. 17-24 [doi]
- SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptanceYiyu Shi, Hao Yu, Lei He. 25-32 [doi]
- Non-gaussian statistical parameter modeling for SSTA with confidence interval analysisLizheng Zhang, Jun Shao, Charlie Chung-Ping Chen. 33-38 [doi]
- introduction to electromigration-aware physical designJens Lienig. 39-46 [doi]
- IC failure mechanisms yesterday, today, tomorrow: implications from test to DFMAnne E. Gattiker. 47 [doi]
- An ::::O::::(::::n::::log::::n::::) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry planeZhe Feng 0002, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan. 48-55 [doi]
- An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstaclesBor-Yiing Su, Yao-Wen Chang, Jiang Hu. 56-63 [doi]
- NEMO: a new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagationHsin-Yu Chen, Zhi-Da Lin. 64-71 [doi]
- Prediction and reduction of routing congestionMehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian. 72-77 [doi]
- Seeing the forest and the trees: Steiner wirelength optimization in placemenJarrod A. Roy, James F. Lu, Igor L. Markov. 78-85 [doi]
- Floorplan and power/ground network co-synthesis for fast design convergenceChen-Wei Liu, Yao-Wen Chang. 86-93 [doi]
- Noise driven in-package decoupling capacitor optimization for power integrityJun Chen, Lei He. 94-101 [doi]
- Efficient decoupling capacitor planning via convex programming methodsAndrew B. Kahng, Bao Liu, Sheldon X.-D. Tan. 102-107 [doi]
- High accurate pattern based precondition method for extremely large power/ground grid analysisJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong. 108-113 [doi]
- Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designsShanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen. 114-119 [doi]
- Efficient generation of short and fast repeater tree topologiesChristoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen. 120-127 [doi]
- Fast buffer insertion considering process variationsJinjun Xiong, Lei He. 128-135 [doi]
- Placement and routing optimization in the brainBeth L. Chen, Dmitri B. Chklovskii. 136-141 [doi]
- Integrated retiming and simultaneous Vdd/Vth scaling for total power minimizationMongkol Ekpanyapong, Sung Kyu Lim. 142-148 [doi]
- Statistical clock tree routing for robustness to process variationsUday Padmanabhan, Janet Meiling Wang, Jiang Hu. 149-156 [doi]
- Variation tolerant buffered clock network synthesis with cross linksAnand Rajaram, David Z. Pan. 157-164 [doi]
- Chip assembly: a new paradigm in hierarchical physical designP. V. Srinivas. 165 [doi]
- Physical design challenges for multi-million gate SoC s: an STMicroelectronics perspectiveFrançois Rémond. 166 [doi]
- ISPD 2006 Placement Contest: Benchmark Suite and ResultsGi-Joon Nam. 167 [doi]
- Clock tree design challenges for robust and low power designArjun Rajagopal. 168 [doi]
- Clockless IC design using handshake technologyAd M. G. Peeters. 169 [doi]
- Solving hard instances of floorplacementAaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran. 170-177 [doi]
- Integrating dynamic thermal via planning with 3D floorplanning algorithmZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. 178-185 [doi]
- Effective linear programming based placement methodsSherief Reda, Amit Chowdhary. 186-191 [doi]
- Improved method of cell placement with symmetry constraints for analog IC layout designShinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi. 192-199 [doi]
- Net cluster: a net-reduction based clustering preprocessing algorithmJianhua Li, Laleh Behjat. 200-205 [doi]
- Satisfying whitespace requirements in top-down placementJarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov. 206-208 [doi]
- Dragon2006: blockage-aware congestion-controlling mixed-size placerTaraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh. 209-211 [doi]
- mPL6: enhanced multilevel mixed-size placementTony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie. 212-214 [doi]
- NTUplace2: a hybrid placer using partitioning and analytical techniquesZhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang. 215-217 [doi]
- A faster implementation of APlaceAndrew B. Kahng, Qinke Wang. 218-220 [doi]