Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen. Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. In Louis Scheffer, editor, Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006. pages 114-119, ACM, 2006. [doi]
Abstract is missing.