Vijay Pitchumani - researchr alias

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Viewing Publication 1 - 35 from 35

2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 coreMoongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim. cicc 2013: 1-4 [doi]

2010

Who solves the variability problem?Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger. dac 2010: 218-219 [doi]

2007

Efficient Thermal via Planning Approach and Its Application in 3-D FloorplanningZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. tcad, 26(4):645-658, 2007. [doi]

2006

Integrating dynamic thermal via planning with 3D floorplanning algorithmZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. ispd 2006: 178-185 [doi]

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integrationZhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani. todaes, 11(2):325-345, 2006. [doi]

Hierarchical 3-D Floorplanning Algorithm for Wirelength OptimizationZhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng. tcas, 53(12):2637-2646, 2006. [doi]

Variation-aware analysis: savior of the nanometer era?Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic. dac 2006: 411-412 [doi]

A Hitchhiker s Guide to the DFM UniverseVijay Pitchumani. apccas 2006: 1103-1106 [doi]

2005

1999

Multi-schedule design space exploration: an alternative synthesis frameworkMehmet Emin Dalkiliç, Vijay Pitchumani. integration, 27(2):87-112, 1999. [doi]

1995

ANSA: A New Neural Net Based Scheduling Algorithm for High Level SynthesisM. Kemal Unaltuna, Vijay Pitchumani. iscas 1995: 385-388

1994

1993

Quadrisectioning Based Placement with a Normalized Mean Field Neural NetworkM. Kemal Unaltuna, Vijay Pitchumani. iscas 1993: 2047-2050

Solving the scheduling problem in high level synthesis using a normalized mean field neural networkM. Kemal Unaltuna, Mehmet Emin Dalkiliç, Vijay Pitchumani. icnn 1993: 275-280 [doi]

1992

Fault simulation on massively parallel SIMD machines algorithms, implementations and resultsVinod Narayanan, Vijay Pitchumani. et, 3(1):79-92, 1992. [doi]

A VHDL Fault Diagnosis Tool Using Functional Fault ModelsVijay Pitchumani, Pankaj Mayor, Nimish Radia. dt, 9(2):33-41, 1992. [doi]

1991

Fault Diagnosis using Functional Fault Models for VHDL descriptionsVijay Pitchumani, Pankaj Mayor, Nimish Radia. itc 1991: 327-337

A System for Fault Diagnosis and Simulation of VHDL DescriptionsVijay Pitchumani, Pankaj Mayor, Nimish Radia. dac 1991: 144-150 [doi]

1989

Restricted symbolic evaluation is fast and usefulJ. Lawrence Carter, Barry K. Rosen, Gordon L. Smith, Vijay Pitchumani. iccad 1989: 38-41 [doi]

Compaction of a Routed Channel on the Connection MachineS. Ganguly, Vijay Pitchumani. dac 1989: 779-782 [doi]

A Massively Parallel Algorithm for Fault Simulation on the Connection MachineVinod Narayanan, Vijay Pitchumani. dac 1989: 734-737 [doi]

1988

: A Parallel Algorithm for Fault Simulation on the Connection MachineVinod Narayanan, Vijay Pitchumani. itc 1988: 89-93

Functional Test Generation Based on Unate Function TheoryVijay Pitchumani, Satish S. Soman. TC, 37(6):756-760, 1988.

1987

A Mixed HVH-VHV Algorithm for Three-Layer Channel RoutingVijay Pitchumani, Qisui Zhang. tcad, 6(4):497-502, 1987. [doi]

1985

Verification of Register Transfer Level Parallel Control SequencesVijay Pitchumani, Edward P. Stabler. TC, 34(8):761-765, 1985.

An Experiment in Programming with Full First-Order LogicZerksis D. Umrigar, Vijay Pitchumani. SLP 1985: 40-47

1983

An Inductive Assertion Method for Register Transfer Level Design VerificationVijay Pitchumani, Edward P. Stabler. TC, 32(12):1073-1080, 1983.

Formal verification of a real-time hardware designZerksis D. Umrigar, Vijay Pitchumani. dac 1983: 221-227 [doi]

1982

A formal method for computer design verificationVijay Pitchumani, Edward P. Stabler. dac 1982: 809-814 [doi]

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