Abstract is missing.
- EDA challenges and options: investing for the futureRuchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok. 1-2 [doi]
- Post-silicon validation challenges: how EDA and academia can helpJagannath Keshava, Nagib Hakim, Chinna Prudvi. 3-7 [doi]
- Post-silicon is too late avoiding the 50 million paperweight starts with validated designsJohn Goodenough, Rob Aitken. 8-11 [doi]
- Post-silicon validation opportunities, challenges and recent advancesSubhasish Mitra, Sanjit A. Seshia, Nicola Nicolici. 12-17 [doi]
- A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layerChia-Jui Hsu, José Luis Pino, Fei-Jiang Hu. 18-23 [doi]
- Abstraction of RTL IPs into embedded softwareNicola Bombieri, Franco Fummi, Graziano Pravadelli. 24-29 [doi]
- Online SystemC emulation accelerationScott Sirowy, Chen Huang, Frank Vahid. 30-35 [doi]
- LATA: a latency and throughput-aware packet processing systemJilong Kuang, Laxmi N. Bhuyan. 36-41 [doi]
- A probabilistic and energy-efficient scheduling approach for online application in real-time systemsThorsten Zitterell, Christoph Scholl. 42-47 [doi]
- Timing analysis of esterel programs on general-purpose multiprocessorsLei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty. 48-51 [doi]
- An effective GPU implementation of breadth-first searchLijuan Luo, Martin D. F. Wong, Wen-mei Hwu. 52-55 [doi]
- Thermal monitoring of real processors: techniques for sensor allocation and full characterizationAbdullah Nazma Nowroz, Ryan Cochran, Sherief Reda. 56-61 [doi]
- Consistent runtime thermal prediction and control through workload phase detectionRyan Cochran, Sherief Reda. 62-67 [doi]
- Adaptive and autonomous thermal tracking for high performance computing systemsYufu Zhang, Ankur Srivastava. 68-73 [doi]
- Non-uniform clock mesh optimization with linear programming buffer insertionMatthew R. Guthaus, Gustavo Wilke, Ricardo Reis. 74-79 [doi]
- Fast timing-model independent buffered clock-tree synthesisXin-Wei Shih, Yao-Wen Chang. 80-85 [doi]
- Clock tree synthesis under aggressive buffer insertionYing-Yu Chen, Chen Dong, Deming Chen. 86-89 [doi]
- Global routing and track assignment for flip-chip designsXiaodong Liu, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng. 90-93 [doi]
- Bridging pre-silicon verification and post-silicon validationAmir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor. 94-95 [doi]
- Compilation and virtualization in the HiPEAC visionChristian Bertin, Christophe Guillon, Koen De Bosschere. 96-101 [doi]
- Processor virtualization and split compilation for heterogeneous multicore embedded systemsAlbert Cohen, Erven Rohou. 102-107 [doi]
- Fine-grained I/O access control based on Xen virtualization for 3G/4G mobile devicesSung-Min Lee, Sang-Bum Suh, Jong-Deok Choi. 108-113 [doi]
- A correlation-based design space exploration methodology for multi-processor systems-on-chipGiovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano. 120-125 [doi]
- Cost-aware three-dimensional (3D) many-core multiprocessor designJishen Zhao, Xiangyu Dong, Yuan Xie. 126-131 [doi]
- Off-chip memory bandwidth minimization through cache partitioning for multi-core platformsChenjie Yu, Peter Petrov. 132-137 [doi]
- Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designersSatyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun. 138-143 [doi]
- Quantifying and coping with parametric variations in 3D-stacked microarchitecturesSerkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel Loh, Alok N. Choudhary. 144-149 [doi]
- Cost-driven 3D integration with interconnect layersXiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li. 150-155 [doi]
- A multilayer nanophotonic interconnection network for on-chip many-core communicationsXiang Zhang, Ahmed Louri. 156-161 [doi]
- Virtual channels vs. multiple physical networks: a comparative analysisYoung-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni. 162-165 [doi]
- An efficient dynamically reconfigurable on-chip network architectureMehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol. 166-169 [doi]
- An AIG-Based QBF-solver using SAT for preprocessingFlorian Pigorsch, Christoph Scholl. 170-175 [doi]
- Analyzing ::::k::::-step induction to compute invariants for SAT-based property checkingMax Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz. 176-181 [doi]
- Coverage in interpolation-based model checkingHana Chockler, Daniel Kroening, Mitra Purandare. 182-187 [doi]
- An efficient algorithm to verify generalized false pathsOlivier Coudert. 188-193 [doi]
- A parallel integer programming approach to global routingTai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth. 194-199 [doi]
- Multi-threaded collision-aware global routing with bounded-length maze routingWen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao. 200-205 [doi]
- Two-sided single-detour untangling for bus routingJin-Tai Yan, Zhi-Wei Chen. 206-211 [doi]
- An optimal algorithm for finding disjoint rectangles and its application to PCB routingHui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong. 212-217 [doi]
- Who solves the variability problem?Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger. 218-219 [doi]
- Joint DAC/IWBDA special session engineering biology: fundamentals and applicationsMarc Riedel, Soha Hassoun, Ron Weiss, Pamela Silver, J. Christopher Anderson, Richard Murray. 220-221 [doi]
- Gate-level characterization: foundations and hardware security applicationsSheng Wei, Saro Meguerdichian, Miodrag Potkonjak. 222-227 [doi]
- SCEMIT: a systemc error and mutation injection toolPeter Lisherness, Kwang-Ting (Tim) Cheng. 228-233 [doi]
- Towards scalable system-level reliability analysisMichael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich. 234-239 [doi]
- Quality metric evaluation of a physical unclonable function derived from an IC s power distribution systemRyan Helinski, Dhruva Acharyya, Jim Plusquellic. 240-243 [doi]
- Theoretical analysis of gate level information flow trackingJason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner. 244-247 [doi]
- Exploiting finite precision information to guide data-flow mappingDavid Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor. 248-253 [doi]
- Robust design methods for hardware accelerators for iterative algorithms in scientific computingAdam B. Kinsman, Nicola Nicolici. 254-257 [doi]
- New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture modelJer Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang. 258-261 [doi]
- Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inferenceWangyang Zhang, Xin Li, Rob A. Rutenbar. 262-267 [doi]
- Speedpath analysis under parametric timing modelsLuÃs Guerra e Silva, Joel R. Phillips, L. Miguel Silveira. 268-273 [doi]
- Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variationsLin Xie, Azadeh Davoodi, Kewal K. Saluja. 274-279 [doi]
- Pulsed-latch aware placement for timing-integrity optimizationYi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang. 280-285 [doi]
- History-based VLSI legalization using network flowMinsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri. 286-291 [doi]
- Performance-driven analog placement considering boundary constraintCheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang. 292-297 [doi]
- 3-D stacked die: now or future?Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic. 298-299 [doi]
- Networks on Chips: from research to productsGiovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini. 300-305 [doi]
- The aethereal network on chip after ten years: goals, evolution, lessons, and futureKees Goossens, Andreas Hansson. 306-311 [doi]
- Automatic multithreaded pipeline synthesis from transactional datapath specificationsEriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam. 314-319 [doi]
- On the costs and benefits of stochasticity in stream processingRaj R. Nadakuditi, Igor L. Markov. 320-325 [doi]
- Performance yield-driven task allocation and scheduling for MPSoCs under process variationLin Huang, Qiang Xu. 326-331 [doi]
- Worst-case response time analysis of resource access models in multi-core systemsAndreas Schranzhofer, Rodolfo Pellizzoni, Jian-Jia Chen, Lothar Thiele, Marco Caccamo. 332-337 [doi]
- A new IP lookup cache for high performance IP routersGuangdeng Liao, Heeyeol Yu, Laxmi N. Bhuyan. 338-343 [doi]
- Instruction cache locking using temporal reuse profileYun Liang, Tulika Mitra. 344-349 [doi]
- Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputationJingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He, Meikang Qiu, Edwin Hsing-Mean Sha. 350-355 [doi]
- SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policyMohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran. 356-361 [doi]
- Fully X-tolerant, very high scan compressionPeter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski. 362-367 [doi]
- BLoG: post-silicon bug localization in processors using bug localization graphsSung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra. 368-373 [doi]
- Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatchNicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir. 374-379 [doi]
- Efficient fault simulation on many-core processorsMichael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin. 380-385 [doi]
- Representative path selection for post-silicon timing prediction under variabilityLin Xie, Azadeh Davoodi. 386-391 [doi]
- QuickYield: an efficient global-search based parametric yield estimation with performance constraintsFang Gong, Hao Yu, Yiyu Shi, DaeSoo Kim, Junyan Ren, Lei He. 392-397 [doi]
- Double patterning lithography aware gridless detailed routing with innovative conflict graphYen-Hung Lin, Yih-Lang Li. 398-403 [doi]
- Frequency domain decomposition of layouts for double dipole lithographyKanak Agarwal. 404-407 [doi]
- Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithographyYongchan Ban, David Z. Pan. 408-411 [doi]
- Does IC design have a future in the clouds?Andreas Kuehlmann, Raul Camposano, James Colgan, John Chilton, Samuel George, Rean Griffith, Paul Leventis, Deepak Singh. 412-414 [doi]
- Automated compact dynamical modeling: an enabling tool for analog designersBradley N. Bond, Luca Daniel. 415-420 [doi]
- Model-based functional verificationKenneth S. Kundert, Henry Chang. 421-424 [doi]
- Fortifying analog models with equivalence checking and coverage analysisMark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao. 425-430 [doi]
- Automated modeling and emulation of interconnect designs for many-core chip multiprocessorsColin J. Ihrig, Rami G. Melhem, Alex K. Jones. 431-436 [doi]
- Trace-driven optimization of networks-on-chip configurationsAndrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam. 437-442 [doi]
- ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chipJason Cong, Chunyue Liu, Glenn Reinman. 443-448 [doi]
- NTPT: on the end-to-end traffic prediction in the on-chip networksYoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng. 449-452 [doi]
- Application-aware NoC design for efficient SDRAM accessWooyoung Jang, David Z. Pan. 453-456 [doi]
- Embedded memory binding in FPGAsKaveh Elizeh, Nicola Nicolici. 457-462 [doi]
- RAMP gold: an FPGA-based architecture simulator for multiprocessorsZhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic. 463-468 [doi]
- Rewiring for robustnessManu Jose, Yu Hu, Rupak Majumdar, Lei He. 469-474 [doi]
- Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysisMingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu. 475-480 [doi]
- A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlationRuijing Shen, Sheldon X.-D. Tan, Jinjun Xiong. 481-486 [doi]
- Synthesis and implementation of active mode power gating circuitsJun Seomun, Insup Shin, Youngsoo Shin. 487-492 [doi]
- Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systemsHeng Yu, Bharadwaj Veeravalli, Yajun Ha. 493-498 [doi]
- BooM: a decision procedure for boolean matching with abstraction and dynamic learningChih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang. 499-504 [doi]
- Node addition and removal in the presence of don t caresYung-Chih Chen, Chun-Yao Wang. 505-510 [doi]
- ECR: a low complexity generalized error cancellation rewiring schemeXiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu. 511-516 [doi]
- LUT-based FPGA technology mapping for reliabilityJason Cong, Kirill Minkovich. 517-522 [doi]
- What s cool for the future of ultra low power designs?Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee. 523-524 [doi]
- Verification for fault tolerance of the IBM system z microprocessorBrian W. Thompto, Bodo Hoppe. 525-530 [doi]
- Formal modeling and reasoning for reliability analysisNatasa Miskov-Zivanov, Diana Marculescu. 531-536 [doi]
- Using introspective software-based testing for post-silicon debug and repairKypros Constantinides, Todd M. Austin. 537-542 [doi]
- Xetal-Pro: an ultra-low energy and high throughput SIMD processorYifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal. 543-548 [doi]
- A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platformsYiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor. 549-554 [doi]
- Scalable effort hardware design: exploiting algorithmic resilience for energy efficiencyVinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar. 555-560 [doi]
- Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulationXiaoji Ye, Peng Li. 561-566 [doi]
- Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysisYong Zhang, Peng Li, Garng M. Huang. 567-572 [doi]
- A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICsXue-Xin Liu, Hao Yu, Sheldon X.-D. Tan. 573-578 [doi]
- Distributed task migration for thermal management in many-core systemsYang Ge, Parth Malani, Qinru Qiu. 579-584 [doi]
- Thermal aware task sequencing on embedded processorsSushu Zhang, Karam S. Chatha. 585-590 [doi]
- A framework for optimizing thermoelectric active cooling systemsJieyi Long, Seda Ogrenci Memik. 591-596 [doi]
- Eyecharts: constructive benchmarking of gate sizing heuristicsPuneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma. 597-602 [doi]
- Detecting tangled logic structures in VLSI netlistsTanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn. 603-608 [doi]
- Lattice-based computation of Boolean functionsMustafa Altun, Marc D. Riedel. 609-612 [doi]
- A novel optimal single constant multiplication algorithmJason Thong, Nicola Nicolici. 613-616 [doi]
- Education panel: designing the always connected car of the futureArkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli, Joseph D Ambrosio, Ed Nuckolls, Harald Wilhelm, Jim Tung, Markus Kuhl, Peter van Staa. 617-618 [doi]
- Find your flow: increasing flow experience by designing human embedded systemsChen-Ling Chou, Anca M. Miron, Radu Marculescu. 619-620 [doi]
- Electronic design automation for social networksAndrew DeOrio, Valeria Bertacco. 621-622 [doi]
- Real time emulations: foundation and applicationsAzalia Mirhoseini, Yousra Alkabani, Farinaz Koushanfar. 623-624 [doi]
- Network on chip design and optimization using specialized influence modelsCristinel Ababei. 625-626 [doi]
- Circuit modeling for practical many-core architecture design explorationDean Truong, Bevan M. Baas. 627-628 [doi]
- Hierarchical hybrid power supply networksFarinaz Koushanfar. 629-630 [doi]
- Detachable nano-carbon chip with ultra low powerShinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong. 631-632 [doi]
- Synthesis of trustable ICs using untrusted CAD toolsMiodrag Potkonjak. 633-634 [doi]
- Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochipsYang Zhao, Krishnendu Chakrabarty. 635-640 [doi]
- Cross-contamination aware design methodology for pin-constrained digital microfluidic biochipsCliff Chiung-Yu Lin, Yao-Wen Chang. 641-646 [doi]
- Reducing the number of lines in reversible circuitsRobert Wille, Mathias Soeken, Rolf Drechsler. 647-652 [doi]
- Synthesis of the optimal 4-bit reversible circuitsOleg Golubitsky, Sean M. Falconer, Dmitri Maslov. 653-656 [doi]
- Crosstalk noise and bit error rate analysis for optical network-on-chipYiyuan Xie, Mahdi Nikdast, Jiang Xu, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu. 657-660 [doi]
- Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysisZhuo Feng, Zhiyu Zeng. 661-666 [doi]
- Stochastic dominant singular vectors method for variation-aware extractionTarek A. El-Moselhy, Luca Daniel. 667-672 [doi]
- Closed-form modeling of layout-dependent mechanical stressVivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David Blaauw. 673-678 [doi]
- Generating parametric models from tabulated dataSanda Lefteriu, Jan Mohring. 679-682 [doi]
- MFTI: matrix-format tangential interpolation for modeling multi-port systemsYuanzhe Wang, Chi-Un Lei, Grantham K. H. Pang, Ngai Wong. 683-686 [doi]
- A universal state-of-charge algorithm for batteriesBingjun Xiao, Yiyu Shi, Lei He. 687-692 [doi]
- A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-taskingMuhammad Adeel Pasha, Steven Derrien, Olivier Sentieys. 693-698 [doi]
- Stacking SRAM banks for ultra low power standby mode operationAdam C. Cabe, Zhenyu Qi, Mircea R. Stan. 699-704 [doi]
- PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation schemeWeixun Wang, Prabhat Mishra. 705-710 [doi]
- In-situ characterization and extraction of SRAM variabilitySrivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark. 711-716 [doi]
- A holistic approach for statistical SRAM analysisPaul Zuber, Petr Dobrovolný, Miguel Miranda. 717-722 [doi]
- Clock tree synthesis with pre-bond testability for 3D stacked IC designsTak-Yung Kim, Taewhan Kim. 723-728 [doi]
- An efficient phase detector connection structure for the skew synchronization systemYu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang. 729-734 [doi]
- What will make your next design experience a much better one?Thomas Harms, Juan-Antonio Caraballo, Reynold D Sa, Ruud A. Haring, Derek Urbaniak, Guntram Wolski, James You. 730 [doi]
- Cyber-physical systems: the next computing revolutionRagunathan Rajkumar, Insup Lee, Lui Sha, John A. Stankovic. 731-736 [doi]
- CPS foundationsEdward A. Lee. 737-742 [doi]
- Medical cyber physical systemsInsup Lee, Oleg Sokolsky. 743-748 [doi]
- Cyber-physical energy systems: focus on smart buildingsJan Kleissl, Yuvraj Agarwal. 749-754 [doi]
- Scalable specification mining for verification and diagnosisWenchao Li, Alessandro Forin, Sanjit A. Seshia. 755-760 [doi]
- Distributed time, conservative parallel logic simulation on GPUsBo D. Wang, Yuhao Zhu, Yangdong Deng. 761-766 [doi]
- An efficient test vector generation for checking analog/mixed-signal functional modelsByong Chan Lim, Jaeha Kim, Mark A. Horowitz. 767-772 [doi]
- Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intentAritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha. 773-776 [doi]
- Efficient simulation of oscillatory combinational loopsMorteza Fayyazi, Laurent Kirsch. 777-780 [doi]
- Transistor sizing of custom high-performance digital circuits with parametric yield considerationsDaniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu. 781-786 [doi]
- RDE-based transistor-level gate simulation for statistical static timing analysisQin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. 787-792 [doi]
- Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilizationVineeth Veetil, Yung-Hsu Chang, Dennis Sylvester, David Blaauw. 793-798 [doi]
- Static timing analysis for flexible TFT circuitsChao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li. 799-802 [doi]
- TSV stress aware timing analysis with applications to 3D-IC layout optimizationJae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan. 803-806 [doi]
- A system for online power prediction in virtualized environments using Gaussian mixture modelsGaurav Dhiman, Kresimir Mihic, Tajana Rosing. 807-812 [doi]
- Performance and power modeling in a multi-programmed multi-core environmentXi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley Mao. 813-818 [doi]
- Reliability aware power management for dual-processor real-time embedded systemsRanjani Sridharan, Rabi N. Mahapatra. 819-824 [doi]
- Recovery-driven design: a power minimization methodology for error-tolerant processor modulesAndrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori. 825-830 [doi]
- Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulationZhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li. 831-836 [doi]
- An efficient dual algorithm for vectorless power grid verification under linear current constraintsXuanxing Xiong, Jia Wang. 837-842 [doi]
- Parallel hierarchical cross entropy optimization for on-chip decap budgetingXueqian Zhao, Yonghe Guo, Zhuo Feng, Shiyan Hu. 843-848 [doi]
- SRAM-based NBTI/PBTI sensor system designZhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan. 849-852 [doi]
- A statistical simulation method for reliability analysis of SRAM core-cellsRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 853-856 [doi]
- What input-language is the best choice for high level synthesis (HLS)?Dan Gajski, Todd M. Austin, Steve Svoboda. 857-858 [doi]
- Stochastic computationNaresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones. 859-864 [doi]
- Best-effort computing: re-thinking parallel software and hardwareSrimat T. Chakradhar, Anand Raghunathan. 865-870 [doi]
- Hardware that produces bounded rather than exact resultsMelvin A. Breuer. 871-876 [doi]
- Impact of process variations on emerging memristorDimin Niu, Yiran Chen, Cong Xu, Yuan Xie. 877-882 [doi]
- Reconfigurable multi-function logic based on graphene P-N junctionsSansiri Tanachutiwat, Ji Ung Lee, Wei Wang, Chun Yung Sung. 883-888 [doi]
- Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancementJie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra. 889-892 [doi]
- Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMSHamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee. 893-896 [doi]
- Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regressionWangyang Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li. 897-902 [doi]
- Behavior-level yield enhancement approach for large-scaled analog circuitsChin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu. 903-908 [doi]
- Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performancesYu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa. 909-912 [doi]
- Pareto sampling: choosing the right weights by derivative pursuitAmith Singhee, Pamela Castalino. 913-916 [doi]
- An error tolerance scheme for 3D CMOS imagersHsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu. 917-922 [doi]
- Fast identification of operating current for toggle MRAM by spiral searchSheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu. 923-928 [doi]
- Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLsLeyi Yin, Peng Li. 929-934 [doi]
- What s smart about the smart grid?Ian A. Hiskens. 937-939 [doi]
- On-die power grids: the missing linkEli Chiprout. 940-945 [doi]