RDE-based transistor-level gate simulation for statistical static timing analysis

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. RDE-based transistor-level gate simulation for statistical static timing analysis. In Sachin S. Sapatnekar, editor, Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010. pages 787-792, ACM, 2010. [doi]

Abstract

Abstract is missing.