Jer Min Jou - researchr alias

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Viewing Publication 1 - 32 from 32

2014

A Transaction-based Design Model and Its MPEG-2 Encoder DesignChun-Yu Chen, Yun-Lung Lee, Jer Min Jou. intcompsymp 2015: 205-214 [doi]

A Run-time Manager for Multithreading of Multi-core SystemsCheng-Hung Hsieh, Jer Min Jou. intcompsymp 2015: 1456-1465 [doi]

2011

Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware SynthesisJer Min Jou, Yun-Lung Lee, Sih-Sian Wu. tcad, 30(8):1184-1196, 2011. [doi]

2010

New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture modelJer Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang. dac 2010: 258-261 [doi]

An Optimal Round-Robin Arbiter Design for NoCJer Min Jou, Yun-Lung Lee. jise, 26(6):2047-2058, 2010. [doi]

Efficient design and generation of a multi-facet arbiterJer Min Jou, Yun-Lung Lee, Sih-Sian Wu. sasp 2010: 111-114 [doi]

2009

A high-speed and decentralized arbiter design for NoCYun-Lung Lee, Jer Min Jou, Yen-Yu Chen. aiccsa 2009: 350-353 [doi]

2007

A Novel Reconfigurable Computation Unit for DSP ApplicationsJer Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun. isvlsi 2007: 439-444 [doi]

2005

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)Yuan-Long Jeang, Jer Min Jou, Win-Hsien Huang. ieicet, 88-A(12):3531-3538, 2005. [doi]

2004

Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting SchemeYeu-Horng Shiau, Jer Min Jou, Chin-Chi Liu. ieicet, 87-D(7):1867-1877, 2004. [doi]

2002

Design of a dynamic pipelined architecture for fuzzy color correctionJer Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen. tvlsi, 10(6):924-929, 2002. [doi]

2001

An efficient blocking-matching algorithm based on fuzzy reasoningPei-Yin Chen, Jer Min Jou. tsmc, 31(2):253-259, 2001.

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting schemeJer Min Jou, Yeu-Horng Shiau, Chin-Chi Liu. iscas 2001: 529-532 [doi]

An efficient VLSI architecture for HMM-based speech recognitionJer Min Jou, Yeu-Horng Shiau, Chen-Jen Huang. icecsys 2001: 469-472 [doi]

2000

Adaptive arithmetic coding using fuzzy reasoning and grey predictionPei-Yin Chen, Jer Min Jou. fss, 114(2):239-254, 2000. [doi]

An adaptive fuzzy logic controller: its VLSI architecture and applicationsJer Min Jou, Pei-Yin Chen, Sheng-Fu Yang. tvlsi, 8(1):52-60, 2000. [doi]

1999

Hazard-Free Synthesis and Decomposition of Asynchronous CircuitsRen-Der Chen, Jer Min Jou, Yeu-Horng Shiau. aspdac 1999: 185-188 [doi]

An efficient method for the decomposition and resynthesis of speed-independent circuitsRen-Der Chen, Jer Min Jou, Yeu-Horng Shiau. icecsys 1999: 339-342 [doi]

A New Pipelined Architecture for Fuzzy Color CorrectionJer Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau. aspdac 1999: 209 [doi]

A fast and efficient lossless data-compression methodJer Min Jou, Pei-Yin Chen. tcom, 47(9):1278-1283, 1999. [doi]

The gray prediction search algorithm for block motion estimationJer Min Jou, Pei-Yin Chen, Jian-Ming Sun. tcsv, 9(6):843-848, 1999. [doi]

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet TransformJer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang. aspdac 1999: 205-208 [doi]

A grey prediction motion estimator for digital image processingJer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun. icecsys 1999: 701-704 [doi]

1997

Diagnostic fault simulation for synchronous sequential circuitsShung-Chih Chen, Jer Min Jou. tcad, 16(3):299-308, 1997. [doi]

Serial diagnostic fault simulation for synchronous sequential circuitsShung-Chih Chen, Jer Min Jou. integration, 23(2):157-170, 1997. [doi]

1995

Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault PartitioningJer Min Jou, Shung-Chih Chen. iscas 1995: 2004-2007

1994

A fast and memory-efficient diagnostic fault simulation for sequential circuitsJer Min Jou, Shung-Chih Chen. iccad 1994: 723-726 [doi]

Multiport Memory Based Data Path Allocation Focusing on Interconnection OptimizationJer Min Jou, Ren-Der Chen, Shiann-Rong Kuang. iscas 1994: 45-48

A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial CircuitsJer Min Jou, Shung-Chih Chen, Ren-Der Chen. iscas 1994: 85-88

1993

Library-Adaptively Integrated Data Path Synthesis for DSP SystemsJer Min Jou, Shiann-Rong Kuang. iccd 1993: 379-382

1990

An Efficient VLSI Switch-Box RouterJer Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang. dt, 7(4):52-65, 1990. [doi]

1989

A new 3-layer rectilinear area router with obstacle avoidanceJer Min Jou, Jau-Yien Lee. integration, 7(1):1-20, 1989. [doi]

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