Table of Contents

• Perturb and simplify: multi-level boolean network optimizerShih-Chieh Chang, Malgorzata Marek-Sadowska. 2-5 [doi]
• Multi-level logic optimization by implication analysisWolfgang Kunz, Premachandran R. Menon. 6-13 [doi]
• Incremental synthesisDaniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain. 14-18 [doi]
• Definition and solution of the memory packing problem for field-programmable systemsDavid Karchmer, Jonathan Rose. 20-26 [doi]
• Integrating program transformations in the memory-based synthesis of image and video algorithmsDavid J. Kolson, Alexandru Nicolau, Nikil D. Dutt. 27-30 [doi]
• Dataflow-driven memory allocation for multi-dimensional signal processing systemsFlorin Balasa, Francky Catthoor, Hugo De Man. 31-34 [doi]
• Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagationUwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold. 36-39 [doi]
• Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0Daniel G. Saab, Youssef Saab, Jacob A. Abraham. 40-43 [doi]
• Analytical fault modeling and static test generation for analog ICsGiri Devarayanadurg, Mani Soma. 44-47 [doi]
• Efficient network flow based min-cut balanced partitioningHonghua Yang, D. F. Wong. 50-55 [doi]
• Multi-way VLSI circuit partitioning based on dual net representationJason Cong, Wilburt Labio, Narayanan Shivakumar. 56-62 [doi]
• A general framework for vertex orderings, with applications to netlist clusteringCharles J. Alpert, Andrew B. Kahng. 63-67 [doi]
• Re-encoding sequential circuits to reduce power dissipationGary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi. 70-73 [doi]
• Precomputation-based sequential logic optimization for low powerMazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou. 74-81 [doi]
• Low power state assignment targeting two-and multi-level logic implementationsChi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain. 82-87 [doi]
• Algorithm selection: a quantitative computation-intensive optimization approachMiodrag Potkonjak, Jan M. Rabaey. 90-95 [doi]
• Adaptation of partitioning and high-level synthesis in hardware/software co-synthesisJörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner. 96-100 [doi]
• Synthesis of concurrent system interface modules with automatic protocol conversion generationBill Lin, Steven Vercauteren. 101-108 [doi]
• An efficient procedure for the synthesis of fast self-testable controller structuresSybille Hellebrand, Hans-Joachim Wunderlich. 110-116 [doi]
• Test pattern generation based on arithmetic operationsSanjay Gupta, Janusz Rajski, Jerzy Tyszer. 117-124 [doi]
• Random pattern testable logic synthesisChen-Huan Chiang, Sandeep K. Gupta. 125-128 [doi]
• Compression-relaxation: a new approach to performance driven placement for regular architecturesAnmol Mathur, C. L. Liu. 130-136 [doi]
• A loosely coupled parallel algorithm for standard cell placementWern-Jieh Sun, Carl Sechen. 137-144 [doi]
• Delay and area optimization for compact placement by gate resizing and relocationWeitong Chuang, Ibrahim N. Hajj. 145-148 [doi]
• Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designsHannah Honghua Yang, D. F. Wong. 150-155 [doi]
• A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arraysNozomu Togawa, Masao Sato, Tatsuo Ohtsuki. 156-163 [doi]
• Universal logic gate for FPGA designChih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin. 164-168 [doi]
• Condition graphs for high-quality behavioral synthesisHsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski. 170-174 [doi]
• Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraintsClaudionor José Nunes Coelho Jr., Giovanni De Micheli. 175-181 [doi]
• Comprehensive lower bound estimation from behavioral descriptionsSeong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt. 182-187 [doi]
• Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristicsAbhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S.-H. Lee. 190-194 [doi]
• VLSI timing simulation with selective dynamic regionizationMeng-Lin Yu, Bryan D. Ackland. 195-199 [doi]
• A new efficient approach to statistical delay modeling of CMOS digital combinational circuitsSyed A. Aftab, M. A. Styblinski. 200-203 [doi]
• Simultaneous driver and wire sizing for performance and power optimizationJason Cong, Cheng-Kok Koh. 206-212 [doi]
• Low-cost single-layer clock trees with exact zero Elmore delay skewAndrew B. Kahng, Chung-Wen Albert Tsao. 213-218 [doi]
• Clock period constrained minimal buffer insertion in clock treesGustavo E. Téllez, Majid Sarrafzadeh. 219-223 [doi]
• Efficient implementation of retimingNarendra V. Shenoy, Richard L. Rudell. 226-233 [doi]
• Retiming with non-zero clock skew, variable register, and interconnect delayTolga Soyata, Eby G. Friedman. 234-241 [doi]
• Optimal latch mapping and retiming within a treeJoel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann. 242-245 [doi]
• Simulation of digital circuits in the presence of uncertaintyMark H. Linderman, Miriam Leeser. 248-251 [doi]
• Fast transient power and noise estimation for VLSI circuitsWolfgang T. Eisenmann, Helmut E. Graeb. 252-257 [doi]
• The Inversion Algorithm for digital simulationPeter M. Maurer. 258-261 [doi]
• Unified complete MOSFET model for analysis of digital and analog circuitsMichiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac. 264-267 [doi]
• A precorrected-FFT method for capacitance extraction of complicated 3-D structuresJ. R. Phillips, J. White. 268-271 [doi]
• Measurement and modeling of MOS transistor current mismatch in analog IC sEric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli. 272-277 [doi]
• Skew sensitivity minimization of buffered clock treeJae Chung, Chung-Kuan Cheng. 280-283 [doi]
• Process-variation-tolerant clock skew minimizationShen Lin, C. K. Wong. 284-288 [doi]
• A specified delay accomplishing clock router using multiple layersMitsuho Seki, Kenji Inoue, Kazuo Kato, Kouki Tsurusaki, Shin ichi Fukasawa, Hitoshi Sasaki, Mutsuhito Aizawa. 289-292 [doi]
• Switching activity analysis considering spatiotemporal correlationsRadu Marculescu, Diana Marculescu, Massoud Pedram. 294-299 [doi]
• Estimation of circuit activity considering signal correlations and simultaneous switchingTan-Li Chou, Kaushik Roy, Sharat Prasad. 300-303 [doi]
• A cell-based power estimation in CMOS combinational circuitsJiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen. 304-309 [doi]
• Design exploration for high-performance pipelinesSmita Bakshi, Daniel D. Gajski. 312-316 [doi]
• Simultaneous functional-unit binding and floorplanningYung-Ming Fang, D. F. Wong. 317-321 [doi]
• Module selection and data format conversion for cost-optimal DSP synthesisKazuhito Ito, Lori E. Lucke, Keshab K. Parhi. 322-329 [doi]
• On testing delay faults in macro-based combinational circuitsIrith Pomeranz, Sudhakar M. Reddy. 332-339 [doi]
• RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faultsAbhijit Chatterjee, Jacob A. Abraham. 340-343 [doi]
• A comprehensive fault macromodel for opampsChen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta. 344-348 [doi]
• Channel-driven global routing with consistent placement (extended abstract)Shigetoshi Nakatake, Yoji Kajitani. 350-355 [doi]
• A new global routing algorithm for FPGAsYao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong. 356-361 [doi]
• On the NP-completeness of regular 2-D FPGA routing architectures and a novel solutionYu-Liang Wu, Douglas Chang. 362-366 [doi]
• A symbolic method to reduce power consumption of circuits containing false pathsR. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi. 368-371 [doi]
• Multi-level network optimization for low powerSasan Iman, Massoud Pedram. 372-377 [doi]
• LP based cell selection with constraints of timing, area, and power consumptionYutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita. 378-381 [doi]
• Power analysis of embedded software: a first step towards software power minimizationVivek Tiwari, Sharad Malik, Andrew Wolfe. 384-390 [doi]
• Generating instruction sets and microarchitectures from applicationsIng-Jer Huang, Alvin M. Despain. 391-396 [doi]
• Register assignment through resource classification for ASIP microcode generationClifford Liem, Trevor C. May, Pierre G. Paulin. 397-402 [doi]
• Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithmRoland W. Freund, Peter Feldmann. 404-411 [doi]
• Capturing time-of-flight delay for transient analysis based on scattering parameter macromodelHaifang Liao, Wayne Wei-Ming Dai. 412-417 [doi]
• RC interconnect synthesis-a moment fitting approachNoel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage. 418-425 [doi]
• Adaptive cut line selection in min-cut placement for large scale sea-of-gates arraysKazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato. 428-431 [doi]
• Folding a stack of equal width componentsVenkat Thanvantri, Sartaj K. Sahni. 432-435 [doi]
• Area minimization for hierarchical floorplansPeichen Pan, Weiping Shi, C. L. Liu. 436-440 [doi]
• Multi-level synthesis for safe replaceabilityCarl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton. 442-449 [doi]
• Iterative algorithms for formal verification of embedded real-time systemsFelice Balarin, Alberto L. Sangiovanni-Vincentelli. 450-457 [doi]
• Incremental formal design verificationGitanjali Swamy, Robert K. Brayton. 458-465 [doi]
• Optimization of critical paths in circuits with level-sensitive latchesTimothy M. Burks, Karem A. Sakallah. 468-473 [doi]
• Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulatorMichel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess. 474-480 [doi]
• Dynamical identification of critical paths for iterative gate sizingHow-Rern Lin, TingTing Hwang. 481-484 [doi]
• Built-in self-test and fault diagnosis of fully differential analogue circuitsSalvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois. 486-490 [doi]
• A new built-in self-test approach for digital-to-analog and analog-to-digital convertersKarim Arabi, Bozena Kaminska, Janusz Rzeszut. 491-494 [doi]
• Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoringGeorges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen. 495-498 [doi]
• An enhanced flow model for constraint handling in hierarchical multi-view design environmentsPieter van der Wolf, K. Olav ten Bosch, Alfred van der Hoeven. 500-507 [doi]
• On modeling top-down VLSI designBernd Schürmann, Joachim Altmeyer, Martin Schütze. 508-515 [doi]
• A formal basis for design process planning and managementMargarida F. Jacome, Stephen W. Director. 516-521 [doi]
• Design of heterogeneous ICs for mobile and personal communication systemsGert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor. 524-531 [doi]
• Embedded systems design for low energy consumptionMichael A. Schuette, John R. Barr. 534-540 [doi]
• Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagramsBill Lin, Srinivas Devadas. 542-549 [doi]
• Performance-driven synthesis of asynchronous controllersKenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas. 550-557 [doi]
• Decomposition methods for library binding of speed-independent asynchronous designsPolly Siegel, Giovanni De Micheli. 558-565 [doi]
• On error correction in macro-based circuitsIrith Pomeranz, Sudhakar M. Reddy. 568-575 [doi]
• Fault dictionary compaction by output sequence removalVamsi Boppana, W. Kent Fuchs. 576-579 [doi]
• Automatic test program generation for pipelined processorsHiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose. 580-583 [doi]
• Synthesis of manufacturable analog circuitsTamal Mukherjee, L. Richard Carley, Rob A. Rutenbar. 586-593 [doi]
• A statistical optimization-based approach for automated sizing of analog cellsF. Medeiro, Francisco V. Fernández, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez. 594-597 [doi]
• Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitationsAlper Demir, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli. 598-603 [doi]
• Improving over-the-cell channel routing in standard cell designXiaolin Liu, Ioannis G. Tollis. 606-609 [doi]
• Minimum crosstalk switchbox routingTong Gao, C. L. Liu. 610-615 [doi]
• Techniques for crosstalk avoidance in the physical design of high-performance digital systemsDesmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli. 616-619 [doi]
• Efficient breadth-first manipulation of binary decision diagramsPranav Ashar, Matthew Cheong. 622-627 [doi]
• Symmetry detection and dynamic variable ordering of decision diagramsShipra Panda, Fabio Somenzi, Bernard Plessier. 628-631 [doi]
• A redesign technique for combinational circuits based on gate reconnectionsYuji Kukimoto, Masahiro Fujita, Robert K. Brayton. 632-637 [doi]
• Non-scan design-for-testability of RT-level data pathsSujit Dey, Miodrag Potkonjak. 640-645 [doi]
• Selecting partial scan flip-flops for circuit partitioningToshinobu Ono. 646-650 [doi]
• Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detectionNur A. Touba, Edward J. McCluskey. 651-654 [doi]
• Macromodeling of analog circuits for hierarchical circuit designJianfeng Shao, Ramesh Harjani. 656-663 [doi]
• Approximate symbolic analysis of large analog integrated circuitsQicheng Yu, Carl Sechen. 664-671 [doi]
• Testing of analog systems using behavioral models and optimal experimental design techniquesEric Felt, Alberto L. Sangiovanni-Vincentelli. 672-678 [doi]
• Layer assignment for high-performance multi-chip modulesKai-Yuan Chao, D. F. Wong. 680-685 [doi]
• The reproducing placement problem with applicationsWei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong. 686-689 [doi]
• RISA: accurate and efficient placement routability modelingChih-Liang Eric Cheng. 690-695 [doi]
• A new approach for factorizing FSM sChunduri Rama Mohan, Partha Pratim Chakrabarti. 698-701 [doi]
• Boolean constrained encoding: a new formulation and a case studyNey Laert Vilar Calazans. 702-706 [doi]
• Optimization of hierarchical designs using partitioning and resynthesisHeinz-Josef Eikerling, Ralf Hunstock, Raul Camposano. 707-712 [doi]
• HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faultsChen-Pin Kung, Chen-Shang Lin. 714-718 [doi]
• Fast timing simulation of transient faults in digital circuitsAbhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel. 719-722 [doi]
• A fast and memory-efficient diagnostic fault simulation for sequential circuitsJer Min Jou, Shung-Chih Chen. 723-726 [doi]
• Timing uncertainty analysis for time-of-flight systemsJohn R. Feehrer, Harry F. Jordan. 728-735 [doi]
• Provably correct high-level timing analysis without path sensitizationSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. 736-742 [doi]
• A timing analysis algorithm for circuits with level-sensitive latchesJin-fuw Lee, Donald T. Tang, C. K. Wong. 743-748 [doi]
• An object-oriented cell library managerNaresh Sehgal, C. Y. Roger Chen, John M. Acken. 750-753 [doi]
• Reuse of design objects in CAD frameworksJoachim Altmeyer, Stefan Ohnsorge, Bernd Schürmann. 754-761 [doi]
• Towards support for design description languages in EDA frameworkOlav Schettler, Susanne Heymann. 762-767 [doi]