Joel Grodstein - researchr alias

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Viewing Publication 1 - 22 from 22

2011

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision ProblemsDesta Tadesse, R. Iris Bahar, Joel Grodstein. et, 27(2):123-136, 2011. [doi]

2009

AutoRex: An automated post-silicon clock tuning toolDesta Tadesse, Joel Grodstein, R. Iris Bahar. itc 2009: 1-10 [doi]

2008

Fast Measurement of the Non-Deterministic Zone in Microprocessor Debug Using Maximum Likelihood EstimationDesta Tadesse, R. Iris Bahar, Joel Grodstein. vts 2008: 339-344 [doi]

2007

Accurate timing analysis using SAT and pattern-dependent delay modelsDesta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein. date 2007: 1018-1023 [doi]

2006

Timing analysis for full-custom circuits using symbolic DC formulationsHui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein. tcad, 25(9):1815-1830, 2006. [doi]

2005

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharingR. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein. tcad, 24(4):502-515, 2005. [doi]

2004

RESTA: a robust and extendable symbolic timing analysis toolKundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein. glvlsi 2004: 407-412 [doi]

2003

Automatic Generation of Critical-Path Tests for a Partial-Scan MicroprocessorJoel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies. iccd 2003: 180-186 [doi]

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage CurrentHui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein. iccd 2003: 70-75 [doi]

2002

1998

1997

Logic decomposition during technology mappingEric Lehman, Yosinatori Watanabe, Joel Grodstein, Heather Harkness. tcad, 16(8):813-834, 1997. [doi]

1995

A delay model for logic synthesis of continuously-sized networksJoel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe. iccad 1995: 458-462 [doi]

Logic decomposition during technology mappingEric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness. iccad 1995: 264-271 [doi]

1994

Optimal latch mapping and retiming within a treeJoel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann. iccad 1994: 242-245 [doi]

1993

A simple algorithm for fanout optimization using high-performance buffer librariesK. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati. iccad 1993: 466-471 [doi]

1991

Automatic Detection of MOS Synchronizers for Timing VerificationJoel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff. iccad 1991: 304-307

Timing Verification on a 1.2M-Device Full-Custom CMOS DesignJengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen. dac 1991: 551-554 [doi]

1990

Constraint Identification for Timing VerificationJoel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen. iccad 1990: 16-19

Race Detection for Two-Phase SystemsJoel Grodstein, Jim Montanaro, Susanne Marino. iccad 1990: 20-23

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