Abstract is missing.
- Metrics for Structural Logic SynthesisPrabhakar Kudva, Andrew Sullivan, William E. Dougherty. 1-6
- Regular Fabrics in Deep Sub-Micron Integrated-Circuit DesignFan Mo, Robert K. Brayton. 7-12
- Topologically Constrained Logic SynthesisSubarnarekha Sinha, Alan Mishchenko, Robert K. Brayton. 13-20
- Optical Realizations of Reversible LogicAnas Al-Rabadi, Lee W. Casperson. 21-26
- Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell PlacementTheodore W. Manikas, Gerald R. Kane. 27-30
- An Approach to Designing Complex Reversible Logic GatesPawel Kerntopf. 31-36
- On Low Power High Level Synthesis Using Genetic AlgorithmsMohamed A. Elgamel, Magdy A. Bayoumi. 37-40
- Equisolvability of Series vs. Controller s Topology in Synchronous Language EquationsNina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli. 45-50
- A Fast Heuristic Algorithm for DisjunctiveTomas Bengtsson, Andrés Martinelli, Elena Dubrova. 51-56
- An Efficient Two-Level Filter Scheme for Low Power CacheYen-Jen Chang, Feipei Lai, Shanq-Jang Ruan. 61-66
- Improving Static Ordering of BDDs for Reachability AnalysisJorgiano Vidal, David Déharbe, Dominique Borrione. 73-77
- Improving Sequential ATPG Using SAT MethodsMukul R. Prasad, Michael S. Hsiao, Jawahar Jain. 79-84
- Nonlinear Sifting of Decision DiagramsPawel Kerntopf. 85-90
- Enhanced SPFD Rewiring on Improving Rewiring AbilityJason Cong, Joey Y. Lin, Wangning Long. 91-96
- A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet ClassificationAmit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz. 97-102
- Field Modifiable Architecture and its Design Methodology: System Design Without Logic SynthesisYoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. 103-108
- Synthesis of Morphable MultipliersSilviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton. 109-113
- Encoding of Boolean Functions and its Application to LUT Cascade SynthesisAlan Mishchenko, Tsutomu Sasao. 115-120
- Technology Mapping for Chemically Assembled Electronic NanotechnologyPetra Färm, Elena Dubrova. 121-124
- Reversible Logic Circuit SynthesisVivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes. 125-130
- ZBDD-Based Backtrack Search SAT SolverFadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah. 131-136
- Efficient Gate and Input Ordering for Circuit-to-BDD ConversionFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 137-142
- Low Power Optimization Techniques for BDD Mapped Finite State MachinesMikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton. 143-148
- A Practical Approach to Cycle Bound Estimation for Property CheckingChia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou. 149-154
- Visualization of Coding Conflicts in Asynchronous Circuit DesignAgnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev. 155-160
- A LUT based Approach for High Level Synthesis on FPGAsLoïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan. 167-172
- A Boolean Paradigm in Multi-Valued Logic SynthesisAlan Mishchenko, Robert K. Brayton. 173-177
- Majority-Based Decomposition of Carry Logic in Binary AddersLeyla Nazhandali, Karem A. Sakallah. 179-184
- Simplifying Constraint Solving in Random Simulation GenerationJun Yuan, Ken Albin, Adnan Aziz, Carl Pixley. 185-190
- Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-NetAnh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin. 191-196
- Logic Synthesis of Reversible Wave CascadesAlan Mishchenko, Marek A. Perkowski. 197-202
- Timing Analysis for Full-Custom Circuits Using Symbolic DC FormulationsHui-Yuan Song, R. Iris Bahar, Joel Grodstein. 203-208
- Efficient Layout Synthesis Algorithm for Pass Transistor Logic CircuitsRupesh S. Shelar, Sachin S. Sapatnekar. 209-214
- A Constructive Matching Algorithm for Library-Based Domino Technology MappingXinning Wang, Prashant Sawkar, Barbara A. Chappell. 215-220
- Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD sFederico Politi. 221-226
- Multi-Level Circuit Clustering for Delay MinimizationCliff C. N. Sze, Ting-Chi Wang. 227-232
- Bi-Decomposition and Tree-Height Reduction for Timing OptimizationJordi Cortadella. 233-238
- Logic Optimization for Asynchronous SI Controllers using Transduction MethodHiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya. 245-250
- On-line Error Detection in a Carry-free AdderWhitney J. Townsend, Mitchell A. Thornton, Parag K. Lala. 251-254
- Reversible Logic Synthesis by Iterative CompositionsAndrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf. 261-266
- Predictability: Definition, Analysis and OptimizationAnkur Srivastava, Majid Sarrafzadeh. 267-272
- Symmetry as a Base for a New Decomposition of Boolean LogicAnas Al-Rabadi. 273-278
- High Throughput Asynchronous Domino Using Dual output BufferMasayuki Tsukisaka, Masashi Imai, Takashi Nanya. 279-282
- Experimental Study on Cell-Base High-Performance Datapath DesignMasanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera. 283-287
- Technology Mapping for Low Leakage Power with Hot-Carrier Effect ConsiderationChang Woo Kang, Massoud Pedram. 295-300
- On the Verification of Sequential EquivalenceJie-Hong Roland Jiang, Robert K. Brayton. 307-314
- Binary Time Frame ExpansionFarzan Fallah. 314-319
- Don t Care Computation in Minimizing Extended Finite State Machines with Presburger ArithmeticYunjian Jiang, Robert K. Brayton. 327-332
- Simplification of Non-Deterministic Multi-Valued NetworksAlan Mishchenko, Robert K. Brayton. 333-338
- Reducing Multi-Valued Algebraic Operations to BinaryJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton. 339-344
- Implicit Test of Regularity for Not Completely Specified Boolean FunctionsAnna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli. 345-350
- A Method for Synthesizing Boolean ConstrainsJun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz. 351-353
- Comparing Transistor-Level Implementations of 4-Input Logic FunctionsFelipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis. 361-365
- Net Buffering in the Presence of Multiple Timing ViewsRajeev Murgai. 367-372
- Overcoming Resolution-Based Lower Bounds for SAT SolversDoRon B. Motter, Igor L. Markov. 373-378
- Comparison of Decision Diagrams for Multiple-Output Logic FunctionsTsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura. 379-384
- VisBDD - A Web-based Visualization Framework for OBDD AlgorithmsChristoph Meinel, Harald Sack, Volker Schillings. 385-390
- Modular Partitioning and Dynamic Conjunction Scheduling in Image ComputationChristoph Meinel, Christian Stangier. 391-396
- Optical Systems 101 for EDA PractitionersJaijeet S. Roychowdhury. 397
- Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-SystemsSteven P. Levitan. 399
- High-Level Synthesis from the Synchronous Language EsterelStephen A. Edwards. 401-406
- Concurrency in System Level Design: Conflict Between Simulation and Synthesis GoalsNick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta. 407-411
- Optimized Power-Delay Curve Generation for Standard Cell ICsMiodrag Vujkovic, Carl Sechen. 413-418
- Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI CircuitsAfshin Abdollahi, Farzan Fallah. 419-424