Chia-Chih Yen - researchr alias

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Viewing Publication 1 - 12 from 12

2020

Embedding Hierarchical Signal to Siamese Network for Fast Name RectificationYi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang. date 2020: 891-896 [doi]

2012

A formal method to improve SystemVerilog functional coverageAn-Che Cheng, Chia-Chih Yen, Jing-Yang Jou. hldvt 2012: 56-63 [doi]

2010

FSM-Based Formal Compliance Verification of Interface ProtocolsChe-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou. jise, 26(5):1601-1617, 2010. [doi]

2008

A General Failure Candidate Ranking Framework for Silicon DebugChia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu. vts 2008: 352-358 [doi]

2006

An Optimum Algorithm for Compacting Error Traces for Efficient Design Error DebuggingChia-Chih Yen, Jing-Yang Jou. TC, 55(11):1356-1366, 2006. [doi]

Diagnosing Silicon Failures Based on Functional Test PatternsChia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu. mtv 2006: 94-98 [doi]

2005

An optimum algorithm for compacting error traces for efficient functional debuggingChia-Chih Yen, Jing-Yang Jou. hldvt 2005: 177-183 [doi]

2004

On compliance test of on-chip bus for SOCHue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou. aspdac 2004: 328-333 [doi]

Enhancing sequential depth computation with a branch-and-bound algorithmChia-Chih Yen, Jing-Yang Jou. hldvt 2004: 3-8 [doi]

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector GenerationChia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen. dt, 21(2):111-120, 2004. [doi]

2002

A Practical Approach to Cycle Bound Estimation for Property CheckingChia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou. iwls 2002: 149-154

2001

Automatic Functional Vector Generation Using the Interacting FSM ModelChien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou. isqed 2001: 372-377 [doi]

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