Abstract is missing.
- System level design technology for realizing an ambient intelligent environmentRudy Lauwereins. 1-3 [doi]
- Fast, predictable and low energy memory references through architecture-aware compilationPeter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig. 4-11 [doi]
- Predictable design of low power systems by pre-implementation estimation and optimizationWolfgang Nebel. 12-17 [doi]
- EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in packageAhmed Amine Jerraya. 18 [doi]
- Abstraction and optimization of consistent floorplanning with pillar block constraintsNing Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani. 19-24 [doi]
- Space-planning: placement of modules with controlled empty area by single-sequenceXuliang Zhang, Yoji Kajitani. 25-30 [doi]
- Layer assignment for reliable system-on-packageJacob R. Minz, Sung Kyu Lim. 31-37 [doi]
- On handling arbitrary rectilinear shape constraintXiaoping Tang, Martin D. F. Wong. 38-41 [doi]
- Robust fixed-outline floorplanning through evolutionary searchChang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang. 42-44 [doi]
- Analog circuit behavioral modeling via wavelet collocation method with auto-compandingJian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou. 45-50 [doi]
- High-level modeling of continuous-time Delta-Sigma A/D-converters using formal modelsEwout Martens, Georges G. E. Gielen. 51-56 [doi]
- High-frequency noise in RF active CMOS mixersPayam Heydari. 57-60 [doi]
- On mismatch in the deep sub-micron era - from physics to circuitsRasit Onur Topaloglu, Alex Orailoglu. 62-67 [doi]
- Register binding and port assignment for multiplexer optimizationDeming Chen, Jason Cong. 68-73 [doi]
- A thread partitioning algorithm in low power high-level synthesisJumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 74-79 [doi]
- Minimization of fractional wordlength on fixed-point conversion for high-level synthesisNobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura. 80-85 [doi]
- A procedure for obtaining a behavioral description for the control logic of a non-linear pipelineHashem Hashemi Najaf-abadi. 86-91 [doi]
- TranGen: a SAT-based ATPG for path-oriented transition faultsKai Yang, Kwang-Ting Cheng, Li-C. Wang. 92-97 [doi]
- Longest path selection for delay test under process variationXiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi. 98-103 [doi]
- SRAM delay fault modeling and test algorithm developmentRei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu. 104-109 [doi]
- An efficient design of non-linear ::::CA:::: based PRPG for VLSI circuit testingSukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri. 110-112 [doi]
- Combinatorial group testing methods for the BIST diagnosis problemAndrew B. Kahng, Sherief Reda. 113-116 [doi]
- Toward mobile phone LinuxYukikazu Nakamoto. 117-124 [doi]
- Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacityYan Wang, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow. 125-130 [doi]
- Rate analysis for streaming applications with on-chip buffer constraintsAlexander Maxiaguine, Simon Künzli, Samarjit Chakraborty, Lothar Thiele. 131-136 [doi]
- Performance-driven global placement via adaptive network characterizationMongkol Ekpanyapong, Sung Kyu Lim. 137-142 [doi]
- Temperature-aware global placementBernd Obermeier, Frank M. Johannes. 143-148 [doi]
- High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiabilityTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 149-154 [doi]
- An integrated approach to timing-driven synthesis and placement of arithmetic circuitsKeoncheol Shin, Taewhan Kim. 155-158 [doi]
- Layer assignment for crosstalk risk minimizationDi Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao. 159-162 [doi]
- CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effectsZhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi. 163-168 [doi]
- NSGA-based parasitic-aware optimization of a 5GHz low-noise VCOMin Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong. 169-174 [doi]
- Analytical expressions for phase noise eigenfunctions of LC oscillatorsPraveen Ghanta, Zheng Li, Jaijeet S. Roychowdhury. 175-180 [doi]
- Analysis of MOS cross-coupled ::::LC::::-tank oscillators using short-channel device equationsMakram M. Mansour, Mohammad M. Mansour, Amit Mehrotra. 181-185 [doi]
- Timing optimization by replacing flip-flops to latchesKo Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura. 186-191 [doi]
- Enhancing the performance of multi-cycle path analysis in an industrial settingHiroyuki Higuchi, Yusuke Matsunaga. 192-197 [doi]
- An approach for reducing dynamic power consumption in synchronous sequential digital designsNoureddine Chabini, Wayne Wolf. 198-204 [doi]
- Low power design using dual threshold voltageYen-Te Ho, TingTing Hwang. 205-208 [doi]
- Technology mapping and packing for coarse-grained, anti-fuse based FPGAsChang Woo Kang, Ali Iranli, Massoud Pedram. 209-211 [doi]
- Efficient RT-level fault diagnosis methodologyOzgur Sinanoglu, Alex Orailoglu. 212-217 [doi]
- Design diagnosis using Boolean satisfiabilityAlexander Smith, Andreas G. Veneris, Anastasios Viglas. 218-223 [doi]
- Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faultsHafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 224-229 [doi]
- Test data compression technique using selective don t-care identificationTerumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase. 230-233 [doi]
- Re-configurable embedded core test protocolSeongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan. 234-237 [doi]
- Object-oriented modeling and synthesis of SystemC specificationsC. Schulz-Key, Markus Winterholer, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel. 238-243 [doi]
- Application of UML for hardware design based on design process modelRobertas Damasevicius, Vytautas Stuikys. 244-249 [doi]
- A cosynthesis algorithm for application specific processors with heterogeneous datapathsYuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 250-255 [doi]
- Design methodology for SoC arthitectures based on reusable virtual coresMichiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada. 256-262 [doi]
- A multiple level network approach for clock skew minimization with process variationsMakoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng. 263-268 [doi]
- Layout techniques for on-chip interconnect inductance reductionShang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang. 269-273 [doi]
- Piecewise quadratic waveform matching with successive chord iterationZhong Wang, Jianwen Zhu. 274-279 [doi]
- Optimal design of high fan-in multiplexers via mixed-integer nonlinear programmingHsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou. 280-283 [doi]
- Adaptive supply voltage technique for low swing interconnectsWoopyo Jeong, Bipul Chandra Paul, Kaushik Roy. 284-287 [doi]
- A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applicationsKyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn. 288-291 [doi]
- Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converterJianhua Gan, Shouli Yan, Jacob A. Abraham. 292-297 [doi]
- Jitter spectral extraction for multi-gigahertz signalChee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang. 298-303 [doi]
- A 35 dB-linear exponential function generator for VGA and AGC applicationsQuoc-Hoang Duong, Sang-Gug Lee. 304-306 [doi]
- A high efficiency 0.5W BTL class-D audio amplifier with RWDM techniqueSimon C. Li, Vincent Chia-Chang Lin. 307-309 [doi]
- Efficient translation of boolean formulas to CNF in formal verification of microprocessorsMiroslav N. Velev. 310-315 [doi]
- Using positive equality to prove liveness for pipelined microprocessorsMiroslav N. Velev. 316-321 [doi]
- On deriving equivalent architecture model from system specificationSamar Abdi, Daniel Gajski. 322-327 [doi]
- On compliance test of on-chip bus for SOCHue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou. 328-333 [doi]
- Opportunities with the open architecture test systemKazumi Hatayama, Rochit Rajsuman. 334 [doi]
- New opportunities with the open architecture test systemRochit Rajsuman. 335 [doi]
- Open architecture tester: what is a key issue of OAT?Yasumasa Nishimura. 336 [doi]
- Open architecture test system: not why but when!Srimat T. Chakradhar. 337-340 [doi]
- New opportunities with the open architecture test systemAdi Merschon. 341 [doi]
- Signal integrity analysis in the open architectureDennis M. Petrich. 342 [doi]
- Opportunities with the open architecture test systemTetsuo Tada. 343 [doi]
- C-based behavioral synthesis and verification analysis on industrial design examplesKazutoshi Wakabayashi. 344-348 [doi]
- Using C based logic synthesis to bridge the productivity gapChris Sullivan, Alex Wilson, Stephen Chappell. 349-354 [doi]
- A place and route aware buffered Steiner tree constructionCliff C. N. Sze, Jiang Hu, Charles J. Alpert. 355-360 [doi]
- An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerationsSampath Dechu, Zion Cien Shen, Chris C. N. Chu. 361-366 [doi]
- Modeling of coplanar waveguide for buffered clock treeJun Chen, Lei He. 367-372 [doi]
- Decode filter cache for energy efficient instruction cache hierarchy in super scalar architecturesKugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya. 373-379 [doi]
- Mixed-clock issue queue design for energy aware, high-performance coresVenkata Syam P. Rapaka, Emil Talpes, Diana Marculescu. 380-383 [doi]
- Power-performance trade-off using pipeline delaysG. Surendra, Subhasis Banerjee, S. K. Nandy. 384-386 [doi]
- Exploiting program execution phases to trade power and performance for media workloadSubhasis Banerjee, G. Surendra, S. K. Nandy. 387-389 [doi]
- LPRAM: a low power DRAM with testabilitySubhasis Bhattacharjee, Dhiraj K. Pradhan. 390-393 [doi]
- Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargetingNuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi. 394-399 [doi]
- Hierarchical extraction and verification of symmetry constraints for analog layout automationSambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi. 400-405 [doi]
- Multi-level placement with circuit schema based clustering in analog IC layoutsTakashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani. 406-411 [doi]
- Model checking on state transition diagramBatsayan Das, Dipankar Sarkar, Santanu Chattopadhyay. 412-417 [doi]
- Efficient reachability checking using sequential SATGanapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang. 418-423 [doi]
- Exploiting state encoding for invariant generation in induction-based property checkingMarkus Wedler, Dominik Stoffel, Wolfgang Kunz. 424-429 [doi]
- Tradeoff routing resource, runtime and quality in buffered routingXiaoping Tang, Martin D. F. Wong. 430-433 [doi]
- Practical methodology of post-layout gate sizing for 15 more power savingNoriyuki Miura, Naoki Kato, Tadahiro Kuroda. 434-437 [doi]
- Interconnect design methods for memory designChanseok Hwang, Massoud Pedram. 438-443 [doi]
- Optimal planning for mesh-based power distributionHongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang. 444-449 [doi]
- 2.5D system integration: a design driven system implementation schemaYangdong (Steven) Deng, Wojciech Maly. 450-455 [doi]
- An HMAC processor with integrated SHA-1 and MD5 algorithmsMao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu. 456-458 [doi]
- Design methodology for IRA codesFrank Kienle, Norbert Wehn. 459-462 [doi]
- Embedded software generation from system level design languagesHaobo Yu, Rainer Dömer, Daniel Gajski. 463-468 [doi]
- Fast and accurate timed execution of high level embedded software using HW/SW interface simulation modelAimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya. 469-474 [doi]
- Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)Aviral Shrivastava, Nikil D. Dutt. 475-477 [doi]
- Memory access driven storage assignment for variables in embedded system designYoonseo Choi, Taewhan Kim. 478-481 [doi]
- MOSFET modeling for RF-CMOS designMitiko Miura-Mattausch. 482-490 [doi]
- RF design methodologies bridging system-IC-module designRobert A. Mullen. 491-498 [doi]
- Hierarchical random-walk algorithms for power grid analysisHaifeng Qian, Sachin S. Sapatnekar. 499-504 [doi]
- A fast decoupling capacitor budgeting algorithm for robust on-chip power deliveryJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan. 505-510 [doi]
- Large-scale linear circuit simulation with an inversed inductance matrixChieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda. 511-516 [doi]
- DEPOGIT: dense power-ground interconnect architecture for physical design integrityAtsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda. 517-522 [doi]
- Design of real-time VGA 3-D image sensor using mixed-signal techniquesYusuke Oike, Makoto Ikeda, Kunihiro Asada. 523-524 [doi]
- A bandwidth and memory efficient MPEG-4 shape encoderKun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen. 525-526 [doi]
- A sub-mW MPEG-4 motion estimation processor core for mobile video applicationYuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. 527-528 [doi]
- Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal visionKimihiro Nishio, Hiroo Yonezu, Shinya Sawa, Yuzo Furukawa. 529-530 [doi]
- 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology nodeTakashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch. 531-532 [doi]
- A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applicationsRamchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo. 533-534 [doi]
- A high efficiency 0.5W BTL class-D audio amplifier with RWDM techniqueSimon C. Li, Vincent Chia-Chang Lin. 535-536 [doi]
- A small-area high-performance 512-point 2-dimensional FFT single-chip processorNaoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi. 537-538 [doi]
- Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS processDongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui. 539-540 [doi]
- A dual-band image-reject mixer for GPS with 64dB image rejectionYoshihiro Utsurogi, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi. 541-542 [doi]
- Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applicationsYuji Yano, Tetsushi Koide, Hans Jürgen Mattausch. 543-544 [doi]
- A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS processTakahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera. 545-546 [doi]
- A reliable low-power fast skew-compensation circuitYi-Ming Wang, Jinn-Shyan Wang. 547-548 [doi]
- A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensorJun Ohta, Tetsuo Furumiya, David C. Ng, Akihiro Uehara, Keiichiro Kagawa, Takashi Tokuda, Masahiro Nunoshita. 549-550 [doi]
- Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processorsTetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka. 551-552 [doi]
- A low power asynchronous Java processor for contactless smart cardChun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-fat Chan, Kong-Pang Pun. 553-554 [doi]
- An image-sensor-based optical receiver fabricated in a standard 0.35-µm CMOS technology for free-space optical communicationsKeiichiro Kagawa, Tomoaki Kawakami, Hiroaki Asazu, Takashi Ikeuchi, Akiko Fujiuchi, Jun Ohta, Masahiro Nunoshita. 555-556 [doi]
- The flexible processor an approach for single-chip hardware emulation by dynamic reconfigurationTakeshi Ohkawa, Toshiyuki Nozawa, Masanori Fujibayashi, Naoto Miyamoto, Leo Karnan, Soichiro Kita, Koji Kotani, Tadahiro Ohmi. 557-558 [doi]
- A dual--band switching digital controller for a buck converterMartin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui. 561-562 [doi]
- Golay and wavelet error control codes in VLSIArunkumar Balasundaram, Angelo Pereira, Jun-Cheol Park, Vincent John Mooney III. 563-564 [doi]
- Timing measurement unit with multi-stage TVC for embedded memoriesKae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang. 565-566 [doi]
- Development of a waveform sampling front-end ASIC for PETJ. Y. Yeom, T. Ishitsu, H. Takahashi. 567-568 [doi]
- A dynamic element matching circuit for multi-bit delta-sigma modulatorsRyozo Katoh, Shin-ya Kobayashi, Takao Waho. 569-570 [doi]
- Design of POP-11 (PDP-11 on programmable chip)Yoshihiro Iida, Naohiko Shimizu. 571-572 [doi]
- A closed caption TV microcontrollerEkachai Leelarasmee, Kanitpong Pengwon. 573-574 [doi]
- Improvement of saturation characteristics of a frequency-demodulation CMOS image sensorJun Ohta, Keiichiro Kagawa, Koichi Yamamoto, Takashi Tokuda, Yu Oya, Masahiro Nunoshita. 575-576 [doi]
- Design and implementation of a secret key steganographic micro-architecture employing FPGAHala A. Farouk, Magdy Saeb. 577-578 [doi]
- Preserving synchronizing sequences of sequential circuits after retimingMaher N. Mneimneh, Karem A. Sakallah, John Moondanos. 579-584 [doi]
- A fast method to derive minimum SOPs for decomposable functionsTsutomu Sasao, Jon T. Butler. 585-590 [doi]
- Efficient computation of canonical form for Boolean matching in large librariesDebatosh Debnath, Tsutomu Sasao. 591-596 [doi]
- Disjoint-support Boolean decomposition combining functional and structural methodsAndrés Martinelli, René Krenz, Elena Dubrova. 597-599 [doi]
- Transduction method for design of logic cell structureKatsunori Tanaka, Yahiko Kambayashi. 600-603 [doi]
- The integration of vehicles into a ubiquitous computing environment computing and networking technologies for vehiclesNaoki Tokitsu. 604-608 [doi]
- Complexity analysis and speedup techniques for optimal buffer insertion with minimum costWeiping Shi, Zhuo Li, Charles J. Alpert. 609-614 [doi]
- A buffer planning algorithm with congestion optimizationSong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu. 615-620 [doi]
- Buffer allocation algorithm with consideration of routing congestionYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu. 621-623 [doi]
- Integrating buffer planning with floorplanning for simultaneous multi-objective optimizationYi-Hui Cheng, Yao-Wen Chang. 624-627 [doi]
- Verification of timed circuits with symbolic delaysRobert Clarisó, Jordi Cortadella. 628-633 [doi]
- Improved symbolic simulation by functional-space decompositionTao Feng, Li-C. Wang, Kwang-Ting Cheng. 634-639 [doi]
- Improving simulation-based verification by means of formal methodsGörschwin Fey, Rolf Drechsler. 640-643 [doi]
- Parallel verilog simulation: architecture and circuit partitionTun Li, Yang Guo, Sikun Li, Fujiang Ao, GongJie Li. 644-646 [doi]
- Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignmentLap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki. 647-652 [doi]
- Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systemsDongkun Shin, Jihong Kim. 653-658 [doi]
- Fast and efficient voltage scheduling by evolutionary slack distributionBita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen. 659-662 [doi]
- Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical dataLap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki. 663-665 [doi]
- A fast congestion estimator for routing with bounded detoursLerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang. 666-670 [doi]
- Accurate and efficient flow based congestion estimation in floorplanningZion Cien Shen, Chris C. N. Chu. 671-676 [doi]
- A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit designJingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu. 677-682 [doi]
- Timing-constrained congestion-driven global routingJin-Tai Yan, Shun-Hua Lin. 683-686 [doi]
- Efficient octilinear Steiner tree construction based on spanning graphsQi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang. 687-690 [doi]
- Representative frequency for interconnect R(f)L(f)C extractionAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. 691-696 [doi]
- A mixed-mode extraction flow for high performance microprocessorsTao Jiang, Eric Pettus, Daksh Lehther. 697-701 [doi]
- An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extractionLiu Yang, Xiaobo Guo, Zeyi Wang. 702-706 [doi]
- Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM methodXiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang. 707-709 [doi]
- Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verificationRouying Zhan, Haigang Feng, Qiong Wu, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang. 710-712 [doi]
- Interconnect capacitance estimation for FPGAsJason Helge Anderson, Farid N. Najm. 713-718 [doi]
- Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restrictionChi-Chou Kao, Yen-Tai Lai. 719-724 [doi]
- Temporal floorplanning using 3D-subTCGPing-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen. 725-730 [doi]
- ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGAYasunori Osana, Tomonori Fukushima, Hideharu Amano. 731-733 [doi]
- SmartGlue: an interface controller with auto reconfiguration for field programmable computing machineYoung-Il Kim, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung. 734-736 [doi]
- An SoC architecture and its design methodology using unifunctional heterogeneous processor arrayYoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera. 737-742 [doi]
- Instruction set and functional unit synthesis for SIMD processor coresNozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki. 743-750 [doi]
- A high performance bus communication architecture through bus splittingRuibing Lu, Cheng-Kok Koh. 751-755 [doi]
- Automatic generation of bus functional models from transaction level modelsDongwan Shin, Samar Abdi, Daniel Gajski. 756-758 [doi]
- A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placementHua Wang, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor. 759-761 [doi]
- Toward stochastic design for digital circuits: statistical static timing analysisShuji Tsukiyama. 762-767 [doi]
- Physical CAD changes to incorporate design for lithography and manufacturabilityLouis Scheffer. 768-773 [doi]
- Parametric reduced order modeling for interconnect analysisGuoyong Shi, C.-J. Richard Shi. 774-779 [doi]
- Realizable parasitic reduction for distributed interconnects using matrix pencil techniqueJanet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang. 780-785 [doi]
- SPICE compatible circuit models for partial reluctance KHao Ji, Qingjian Yu, Wayne Wei-Ming Dai. 786-791 [doi]
- Frequency-dependent reluctance extractionClement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen. 792-797 [doi]
- Future reconfigurable computing systemMasahiko Kawamura, Hideharu Amano. 798 [doi]
- Enabling on-chip diversity through architectural communication designTudor Dumitras, Sam Kerner, Radu Marculescu. 799-805 [doi]
- Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptationYoung-Su Kwon, Jae-Gon Lee, Chong-Min Kyung. 806-811 [doi]
- A novel memory size model for variable-mapping in system level designLukai Cai, Haobo Yu, Daniel Gajski. 812-817 [doi]
- A compressed frame buffer to reduce display power consumption in mobile systemsHojun Shim, Naehyuck Chang, Massoud Pedram. 818-823 [doi]
- Instruction buffering exploration for low energy VLIWs with instruction clustersTom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal. 824-829 [doi]
- A static and dynamic energy reduction technique for I-cache and BTB in embedded processorsHidenori Sato, Toshinori Sato. 830-833 [doi]
- Resource-constrained low-power bus encoding with crosstalk delay eliminationMeeyoung Cha, Chun-Gi Lyuh, Taewhan Kim. 834-837 [doi]
- Compiler based exploration of DSP energy savings by SIMD operationsMarkus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers. 838-841 [doi]
- Synthesizable HDL generation method for configurable VLIW processorsYuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 842-845 [doi]
- A non-iterative model for switching window computation with crosstalk noiseJanet Meiling Wang, Omar Hafiz, Pinhong Chen. 846-851 [doi]
- Gate delay calculation considering the crosstalk capacitancesSoroush Abbaspour, Massoud Pedram. 852-857 [doi]
- A simplified transmission-line based crosstalk noise model for on-chip RLC wiringKanak Agarwal, Dennis Sylvester, David Blaauw. 858-864 [doi]
- Minimization of the expected path length in BDDs based on local changesRüdiger Ebendt, Wolfgang Günther, Rolf Drechsler. 865-870 [doi]
- Minimization of memory size for heterogeneous MDDsShinobu Nagayama, Tsutomu Sasao. 871-874 [doi]
- Combining ordered best-first search with branch and bound for exact BDD minimizationRüdiger Ebendt, Wolfgang Günther, Rolf Drechsler. 875-878 [doi]
- Satisfiability and integer programming as complementary toolsRuiming Li, Dian Zhou, Donglei Du. 879-882 [doi]
- ShatterPB: symmetry-breaking for pseudo-Boolean formulasFadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah. 883-886 [doi]
- Automatic process migration of datapath hard IP librariesFang Fang, Jianwen Zhu. 887-892 [doi]
- Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessorYiran Chen, Kaushik Roy, Cheng-Kok Koh. 893-898 [doi]
- High-level area and power-up current estimation considering rich cell libraryFei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy. 899-904 [doi]