Tsin-Yuan Chang - researchr alias

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Viewing Publication 1 - 36 from 36

2019

A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color DisplayChih-Wen Lu, Pei-Yi Lai Lee, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou, Poki Chen, Tsin-Yuan Chang, Jenny Yi-Chun Liu. jssc, 54(10):2703-2716, 2019. [doi]

2014

2012

2011

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder TreeYuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li. tvlsi, 19(4):709-714, 2011. [doi]

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation BiasYuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang. esticas, 1(3):277-288, 2011. [doi]

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT ApplicationsChung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen. tcas, 58-II(4):215-219, 2011. [doi]

2010

Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang. tcad, 29(11):1837-1842, 2010. [doi]

A 2.4-GS/s FFT Processor for OFDM-Based WPAN ApplicationsSong-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang. tcas, 57-II(6):451-455, 2010. [doi]

2009

IEEE Standard 1500 Compatible Delay Test FrameworkPo-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang. tvlsi, 17(8):1152-1156, 2009. [doi]

2008

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AESChung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang. isvlsi 2008: 503-506 [doi]

A current mode adaptive on-time control scheme for fast transient DC-DC convertersHung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang. iscas 2008: 2602-2605 [doi]

An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response ImprovementHung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang. tcas, 55-II(9):853-857, 2008. [doi]

2006

A chaos-based pseudo random number generator using timing-based reseeding methodChung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang. iscas 2006: [doi]

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency RangeChung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang. ats 2006: 313-317 [doi]

2005

On-chip accumulated jitter measurement for phase-locked loopsChih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang. aspdac 2005: 1184-1187 [doi]

2004

A Built-In Parametric Timing Measurement UnitMing-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang. dt, 21(4):322-330, 2004. [doi]

Timing measurement unit with multi-stage TVC for embedded memoriesKae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang. aspdac 2004: 565-566 [doi]

A Measurement Unit for Input Signal Analysis of SRAM Sense AmplifierYi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang. ats 2004: 272-276 [doi]

2003

A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column driversShao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong. iscas 2003: 365-368 [doi]

2002

An Embedded Built-In-Self-Test Approach for Analog-to-Digital ConvertersSheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang. ats 2002: 266 [doi]

An Access Timing Measurement Unit of Embedded MemoryShu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang. ats 2002: 104 [doi]

2001

A low-cost CMOS time interval measurement coreMing-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang. iscas 2001: 190-193 [doi]

A built-in timing parametric measurement unitMing-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang. itc 2001: 315-322

An Embedded Built-in-Self-Test Approach for Digital-to-Analog ConvertersJeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang. ats 2001: 423 [doi]

2000

SoC Testing and P1500 StandardTsin-Yuan Chang, Yervant Zorian. ats 2000: 492 [doi]

A realistic fault model for flash memoriesYea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang. ats 2000: 274-281 [doi]

1999

A Programmable BIST Core for Embedded DRAMChih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang. dt, 16(1):59-70, 1999. [doi]

1992

A design for concurrent error detections in FPLAsTsin-Yuan Chang, Jean-Bean Hsu, Cheng Chi Wang, Yu Shen Lin. glvlsi 1992: 9-15 [doi]

1990

An efficient output phase assignment for PLA minimizationChin-Long Wey, Tsin-Yuan Chang. tcad, 9(1):1-7, 1990. [doi]

Design of Repairable and Fully Diagnosable Folded PLAs for Yield EnhancementChin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang. dac 1990: 327-332 [doi]

1988

PLAYGROUND: Minimization of PLAs with Mixed Ground True OutputsChin-Long Wey, Tsin-Yuan Chang. dac 1988: 421-426 [doi]

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