Abstract is missing.
- Adaptive Reliable Chips - Reconfigurable Computing in the Nano EraJürgen Becker. 1-2 [doi]
- Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching MemoriesChristophe Muller. 3 [doi]
- Arithmetic Data Path Optimization Using Borrow-Save RepresentationSophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. 4-9 [doi]
- Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer DesignOmid Kavehie, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha. 10-15 [doi]
- Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor DesignZhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann. 16-21 [doi]
- Determining the Optimal Number of Islands in Power Islands SynthesisDeniz Dal, Nazanin Mansouri. 22-27 [doi]
- Defect Tolerance Inspired by Artificial EvolutionAsbjørn Djupdal, Pauline C. Haddow. 28-33 [doi]
- Reliability of n-Bit Nanotechnology AdderIsmo Hänninen, Jarmo Takala. 34-39 [doi]
- Spintronic Device Based Non-volatile Low Standby Power SRAMWeisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer. 40-45 [doi]
- Application of Bottom-Up Methodology to RTW VCOFahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod. 46-50 [doi]
- A Closed-Loop Architecture with Digital Output for Convective AccelerometersOlivier Leman, Laurent Latorre, Frédérick Mailly, Pascal Nouet. 51-56 [doi]
- A CMOS Multi-sensor System for 3D Orientation DeterminationBoris Alandry, Norbert Dumas, Laurent Latorre, Frédérick Mailly, Pascal Nouet. 57-62 [doi]
- FSMD Partitioning for Low Power Using ILPNainesh Agarwal, Nikitas J. Dimopoulos. 63-68 [doi]
- Uncriticality-Directed Low-Power Instruction SchedulingShingo Watanabe, Toshinori Sato. 69-74 [doi]
- Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge DevicesKarthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan D. George. 75-80 [doi]
- BTB Access Filtering: A Low Energy and High Performance DesignShuai Wang, Jie Hu, Sotirios G. Ziavras. 81-86 [doi]
- A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic ApplicationsRalf Laue 0002, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena. 87-92 [doi]
- System Level Design Space Exploration for Multiprocessor System on ChipIssam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid. 93-98 [doi]
- A Novel System-Level On-Chip Resource Allocation Method for Manycore ArchitecturesTheocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar. 99-104 [doi]
- MPI-Based Adaptive Task Migration Support on the HS-Scale SystemNicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert. 105-110 [doi]
- Low Power High Performance Digitally Assisted Pipelined ADCBahar Jalali Farahani, Anand Meruva. 111-116 [doi]
- A Novel Low-Power Clock Skew Compensation CircuitRong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng. 117-121 [doi]
- High Speed Ultra Low Voltage CMOS inverterYngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet. 122-127 [doi]
- A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error DetectionLingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas. 128-133 [doi]
- Process Algebra Based SoC Test Scheduling for Test Time MinimizationJingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang. 134-138 [doi]
- Improving the Test of NoC-Based SoCs with Help of Compression SchemesJulien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre. 139-144 [doi]
- A Novel System on Chip (SoC) Test SolutionMichael Higgins, Ciaran MacNamee, Brendan Mullane. 145-150 [doi]
- Testing Skew and Logic Faults in SoC InterconnectsNestor Hernandez, Víctor H. Champac. 151-156 [doi]
- A Programmable Frequency Divider in 0.18µm CMOS LibraryQingsheng Hu, Hua-An Zhao, Chen Liu. 157-161 [doi]
- Energy Recovery from High-Frequency Clocks Using DC-DC ConvertersMehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William Dunford, Patrick Palmer. 162-167 [doi]
- Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLLXiao Pu, Axel Thomsen, Jacob Abraham. 168-172 [doi]
- Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless ApplicationsAhmed El Oualkadi, Denis Flandre. 173-178 [doi]
- Impact of Technology Scaling on Digital Subthreshold CircuitsDavid Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat. 179-184 [doi]
- Low Standby Power and Robust FinFET Based SRAM DesignBehzad Ebrahimi, Saeed Zeinolabedinzadeh, Ali Afzali-Kusha. 185-190 [doi]
- CMOS Control Enabled Single-Type FET NASICPritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz. 191-196 [doi]
- A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing EnginesV. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi. 197-202 [doi]
- Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode SelectionGrzegorz Pastuszak. 203-208 [doi]
- Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication ApplicationsAli Ahmadinia, Balal Ahmad, Tughrul Arslan. 209-214 [doi]
- Performance Improvement of Physical Retiming with Shortcut InsertionAdel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani. 215-220 [doi]
- A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage VariationYibo Wang, Yici Cai, Xianlong Hong. 221-226 [doi]
- A New Clock Mesh Buffer Sizing Methodology for Skew and Power ReductionGustavo Wilke, Ricardo Reis. 227-232 [doi]
- An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction SchemeArash Mehdizadeh, Morteza Saheb Zamani, H. Shafiei. 233-238 [doi]
- A Real Case of Significant Scan Test Cost ReductionSelina Sha, Bruce Swanson. 239-244 [doi]
- A Network Based Functional Verification Method of IEEE 1394a PHY CoreColin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan. 245-250 [doi]
- Cohesive Coverage Management for Simulation and Formal Property VerificationAritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan. 251-256 [doi]
- Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft ErrorsIlia Polian, Sudhakar M. Reddy, Bernd Becker. 257-262 [doi]
- Memory Power Modeling - A Novel ApproachAjit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar. 263-268 [doi]
- Integrated Power-Gating and State Assignment for Low Power FSM SynthesisSambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay. 269-274 [doi]
- Efficient High-Level Power Estimation for Multi-standard Wireless SystemsAli Ahmadinia, Balal Ahmad, Tughrul Arslan. 275-280 [doi]
- Modeling and Optimization of Switching Power Dissipation in Static CMOS CircuitsAdnan Kabbani. 281-285 [doi]
- Core Allocation and Relocation Management for a Self Dynamically Reconfigurable ArchitectureMassimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto. 286-291 [doi]
- SeReCon: A Secure Dynamic Partial Reconfiguration ControllerKrzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz. 292-297 [doi]
- GePaRD - A High-Level Generation Flow for Partially Reconfigurable DesignsMaik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke. 298-303 [doi]
- Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAsKatarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker. 304-309 [doi]
- Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability AspectsMichael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. 310-315 [doi]
- Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierBettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard. 316-321 [doi]
- Characterisation of FPGA Clock VariabilityN. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. 322-328 [doi]
- A Fuzzy Approach for Variation Aware Buffer Insertion and Driver SizingVenkataraman Mahalingam, Nagarajan Ranganathan. 329-334 [doi]
- Flow Maximization for NoC Routing AlgorithmsYing-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen. 335-340 [doi]
- Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-ChipEverton Carara, Fernando Gehm Moraes. 341-346 [doi]
- Hermes-GLP: A GALS Network on Chip Router with Power Control TechniquesJulian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans. 347-352 [doi]
- Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance AmplifierV. Suresh Babu, Katharine A. A. Rose, M. R. Baiju. 353-356 [doi]
- A Versatile Linear Insertion Sorter Based on a FIFO SchemeRoberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe. 357-362 [doi]
- Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration SelectionHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. 363-368 [doi]
- Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and ObservationsPrasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta. 369-374 [doi]
- Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game TheoryDiego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 375-380 [doi]
- Standard Cell Like Via-Configurable Logic Block for Structured ASICsMei-Chen Li, Hui-Hsiang Tung, Chien-chung Lai, Rung-Bin Lin. 381-386 [doi]
- SDVM-R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-ChipAndreas Hofmann, Klaus Waldschmidt. 387-392 [doi]
- Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning SchemeMohamed B. Abdelhalim, Serag E.-D. Habib. 393-398 [doi]
- FPGA-Based Circuit Model Emulation of Quantum AlgorithmsMahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi. 399-404 [doi]
- Petri Net Based Rapid Prototyping of Digital Complex SystemDavid Andreu, Guillaume Souquet, Thierry Gil. 405-410 [doi]
- Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean SatisfiabilityRobert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler. 411-416 [doi]
- A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level SynthesisFabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto. 417-422 [doi]
- Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level SynthesisHariharan Sankaran, Srinivas Katkoori. 423-428 [doi]
- Efficient Realization of Strongly Indicating Function BlocksPadnamabhan Balasubramanian, D. A. Edwards. 429-432 [doi]
- Virtual Point-to-Point Links in Packet-Switched NoCsMehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol. 433-436 [doi]
- Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-ChipMasud H. Chowdhury, Juliana Gjanci, Pervez Khaled. 437-440 [doi]
- A Web Server Based Edge Detector Implementation in FPGASunil Shukla, Neil W. Bergmann, Jürgen Becker. 441-446 [doi]
- Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare WaysMaziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara. 447-450 [doi]
- In Situ Design of Register OperationsSerge Burckel, Emeric Gioan. 451-454 [doi]
- An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture DesignHongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren. 455-458 [doi]
- Raising the Level of Abstraction for the Timing Verification of System-on-ChipsRupsa Chakraborty, Dipanwita Roy Chowdhury. 459-462 [doi]
- Power Modeling in SystemC at Transaction Level, Application to a DVFS ArchitectureHugo Lebreton, Pacal Vivet. 463-466 [doi]
- Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield ImprovementMinoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi. 467-470 [doi]
- Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible FunctionsYasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani. 471-474 [doi]
- NoC Power Estimation at the RTL Abstraction LevelGuilherme Guindani, Cezar Reinbrecht, T. Raupp, Ney Calazans, Fernando Gehm Moraes. 475-478 [doi]
- Design of Fractal Image Compression on SOCAhmed Jedidi, Badreddine Rejeb, Mohamed Abid. 479-482 [doi]
- A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular MultiplierJin-Hua Hong, Wen-Jie Li. 483-486 [doi]
- A Neural Stimulator Output Stage for Dodecapolar ElectrodesFabien Soulier, Jean-Baptiste Lerat, Lionel Gouyet, Serge Bernard, Guy Cathébras. 487-490 [doi]
- Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip InterconnectsLeandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner. 491-494 [doi]
- Finding the Best Compromise in Compiling Compound Loops to VerilogYosi Ben-Asher, Eddie Shochat. 495-498 [doi]
- An Auto-adaptation Method for Dynamically Reconfigurable System-on-ChipXun Zhang, Hassan Rabah, Serge Weber. 499-502 [doi]
- An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AESChung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang. 503-506 [doi]
- Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threadingMehrdad Najibi, Hossein Pedram. 507-510 [doi]
- A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic MemoryDaisaku Seto, Minoru Watanabe. 511-514 [doi]