Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi. Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 467-470, IEEE Computer Society, 2008. [doi]
Abstract is missing.