Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement - researchr publication authors

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Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi. Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 467-470, IEEE Computer Society, 2008. [doi]

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