Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi. Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 467-470, IEEE Computer Society, 2008. [doi]
@inproceedings{MirsaeediZS08, title = {Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement}, author = {Minoo Mirsaeedi and Morteza Saheb Zamani and Mehdi Saeedi}, year = {2008}, doi = {10.1109/ISVLSI.2008.69}, url = {http://dx.doi.org/10.1109/ISVLSI.2008.69}, researchr = {https://researchr.org/publication/MirsaeediZS08}, cites = {0}, citedby = {0}, pages = {467-470}, booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France}, publisher = {IEEE Computer Society}, }