Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture - researchr publication

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Hugo Lebreton, Pacal Vivet. Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 463-466, IEEE Computer Society, 2008. [doi]

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