Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Hugo Lebreton, Pacal Vivet. Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 463-466, IEEE Computer Society, 2008. [doi]

This author has not been identified. Look up 'Hugo Lebreton' in GoogleThis author has not been identified. Look up 'Pacal Vivet' in Google

runs on WebDSL