Hugo Lebreton, Pacal Vivet. Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 463-466, IEEE Computer Society, 2008. [doi]
@inproceedings{LebretonV08,
title = {Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture},
author = {Hugo Lebreton and Pacal Vivet},
year = {2008},
doi = {10.1109/ISVLSI.2008.71},
url = {http://dx.doi.org/10.1109/ISVLSI.2008.71},
tags = {modeling, architecture},
researchr = {https://researchr.org/publication/LebretonV08},
cites = {0},
citedby = {0},
pages = {463-466},
booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France},
publisher = {IEEE Computer Society},
}