Abstract is missing.
- AC-JTAG: empowering JTAG beyond testing DC netsSung Soo Chung, Sanghyeon Baeg. 30-37
- A general purpose 1149.4 IC with HF analog test capabilitiesStephen K. Sunter, Ken Filliter, Joe Woo, Pat McHugh. 38-45
- Frequency detection-based boundary-scan testing of AC coupled netsYoung Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick. 46-53
- Design of compactors for signature-analyzers in built-in self-testPeter Wohl, John A. Waicukauski, Thomas W. Williams. 54-63
- At-speed logic BIST using a frozen clock testing strategyJongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici. 64-71
- Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipationNicola Nicolici, Bashir M. Al-Hashimi. 72-81
- Improved wafer-level spatial analysis for I_DDQ limit settingSagar S. Sabade, D. M. H. Walker. 82-91
- Neighbor selection for variance reduction in I_DDQ and other parametric dataW. Robert Daasch, Kevin Cota, James McNames, Robert Madge. 92-100
- The future of delta I_DDQ testingBram Kruseman, Rudger van Veen, Kees van Kaam. 101-110
- A building block BIST methodology for SOC designs: a case studyPatrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre. 111-120
- Test and debug strategy of the PNX8525 Nexperia:::TM::: digital video platform system chipBart Vermeulen, Steven Oostdijk, Frank Bouwman. 121-130
- CTL the language for describing core-based testRohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay. 131-139
- Split timing mode (STM)-answer to dual frequency domain testingA. T. Sivaram. 140-147
- Automated translation of legacy code for ATEAndrew Moran, Jim Teisher, Andy Gill, Emir Pasalic, John Veneruso. 148-156
- Remote access to engineering test-a case study in providing engineering/diagnostic IC test services to Canadian universitiesR. L. Stevenson, M. E. Jarosz, C. V. Verver. 157-162
- Test and repair of large embedded DRAMs. IRoderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey Dreibelbis. 163-172
- Test and repair of large embedded DRAMs. 2Eric A. Nelson, Jeffrey Dreibelbis, Roderick McConnell. 173-181
- Test cost reduction by at-speed BISR for embedded DRAMsYoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada. 182-187
- DPDAT: data path direct access testingKee Sup Kim, Rathish Jayabharathi, Craig Carstens, Praveen Vishakantaiah, Derek Feltham, Adrian Carbine. 188-195
- A method to enhance the fault coverage obtained by output response comparison of identical circuitsIrith Pomeranz, Sudhakar M. Reddy. 196-203
- Contactless digital testing of IC pin leakage currentsStephen K. Sunter, Charles McDonald, Givargis Danialy. 204-210
- On improving the stuck-at fault coverage of functional test sequences by using limited-scan operationsIrith Pomeranz, Sudhakar M. Reddy. 211-220
- Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection techniqueKaijie Wu, Ramesh Karri. 221-229
- A highly-efficient transparent online memory testKarl Thaller. 230-239
- On-line testing and recovery in TMR systems for real-time applicationsShu-Yi Yu, Edward J. McCluskey. 240-249
- GRAAL: a tool for highly dependable SRAMs generationSilvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari. 250-257
- Test response compression and bitmap encoding for embedded memories in manufacturing process monitoringJohn T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly. 258-267
- A technique for fault diagnosis of defects in scan chainsRuifeng Guo, Srikanth Venkataraman. 268-277
- Making cause-effect cost effective: low-resolution fault dictionariesDavid B. Lavo, Tracy Larrabee. 278-286
- Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigmThomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski. 287-296
- Testing gigabit multilane SerDes interfaces with passive jitter injection filtersBernd Laquai, Yi Cai. 297-304
- Testing interconnects for noise and skew in gigahertz SoCsAmir Attarha, Mehrdad Nourani. 305-314
- A built-in timing parametric measurement unitMing-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang. 315-322
- Testing clock distribution circuits using an analytic signal methodTakahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida. 323-331 [doi]
- Rapid prototyping of time-based PDIT for substrate networks [MCM] Aranggan Venkataratnam, Kimberly E. Newman. 332-339
- Estimating burn-in fall-out for redundant memoryThomas S. Barnett, Adit D. Singh, Victor P. Nelson. 340-347
- Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancementMohammad Athar Khalil, Chin-Long Wey. 348-357
- Multiple-output propagation transition fault testChao-Wen Tseng, Edward J. McCluskey. 358-366
- Switch-level delay test of domino logic circuitsSuriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer. 367-376
- Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-levelFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 377-385
- Practical application of energy consumption ratio testErik Peterson, Wanli Jiang. 386-394
- Detecting delay faults using power supply transient signal analysisAbhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker. 395-404
- A practical built-in current sensor for I_DDQ testingHoki Kim, D. M. H. Walker, David Colby. 405-414
- Test path simulation and characterisationKlaus Helmreich. 415-423
- Testing beyond EPA: TDF methodology solutions matrixSunil K. Jain, Greg P. Chema. 424-432
- Practical, non-invasive optical probing for flip-chip devicesG. Dajee, N. Goldblatt, T. Lundquist, S. Kasapi, Keneth R. Wilsher. 433-442
- Scan vs. functional testing - a comparative effectiveness study on Motorola s MMC2107:::TM:::Ken Tumin, Carmen Vargas, Ross Patterson, Chris Nappi. 443-450
- Debug methodology for the McKinley processorDon Douglas Josephson, Steve Poehhnan, Vincent Govan. 451-460
- Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testabilityMichael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich. 461-469
- Testing and programming flash memories on assemblies during high volume productionF. G. M. de Jong, Alex S. Biewenga, D. C. L. van Geest, T. F. Waayers. 470-479
- Hierarchical boundary-scan: a Scan Chip-Set solutionStephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood. 480-486
- A practical guide to combining ICT & boundary scan testingAlan Albee. 487-494
- Ramp testing of ADC transition levels using finite resolution rampsSolomon Max. 495-501
- Test challenges for SONET/SDH physical layer OC3 devices and beyondUdaya Natarajan. 502-511
- A method to improve SFDR with random interleaved sampling methodMamoru Tamba, Atsushi Shimizu, Hideharu Munakata, Takanori Komuro. 512-520
- Space and time compaction schemes for embedded coresOzgur Sinanoglu, Alex Orailoglu. 521-529
- Tailoring ATPG for embedded testingRainer Dorsch, Hans-Joachim Wunderlich. 530-537
- A case study on the implementation of the Illinois Scan ArchitectureFrank F. Hsu, Kenneth M. Butler, Janak H. Patel. 538-547
- Crosstalk test generation on pseudo industrial circuits: a case studyLiang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer. 548-557
- Delay testing considering crosstalk-induced effectsAngela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng. 558-567
- On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuitsKeith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu. 568-577
- Test methodology for the McKinley processorDon Douglas Josephson, Steve Poehlman, Vincent Govan, Clint Mumford. 578-585
- 99 AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 MicroprocessorMary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott. 586-592
- Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for NintendoGilbert Vandling. 593-599
- Towards a unified test process: from UML to end-of-line functional testAndrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei. 600-608
- Dynamic tests in complex systems [automotive electronics]Robert Tappe, Dietmar Ehrhardt. 609-614
- Unsafe board states during PC-based boundary-scan testingWilliam Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo. 615-623
- Too much delay fault coverage is a bad thingJeff Rearick. 624-633
- Testing of critical paths for delay faultsManish Sharma, Janak H. Patel. 634-641
- Exact path delay grading with fundamental BDD operationsSaravanan Padmanaban, Maria K. Michael, Spyros Tragoudas. 642-651
- Scan array solution for testing power and testing timeLei Xu, Yihe Sun, Hongyi Chen. 652-659
- A token scan architecture for low power testingTsung-Chu Huang, Kuen-Jong Lee. 660-669
- An analysis of power reduction techniques in scan testingJayashree Saxena, Kenneth M. Butler, Lee Whetsel. 670-677
- On efficient error diagnosis of digital circuitsNandini Sridhar, Michael S. Hsiao. 678-687
- A study of bridging defect probabilities on a Pentium (TM) 4 CPUVenkatram Krishnaswamy, A. B. Ma, Praveen Vishakantaiah. 688-695
- FedEx - a fast bridging fault extractorZoran Stanojevic, D. M. H. Walker. 696-703
- Power supply transient signal integration circuitChintan Patel, Fidel Muradali, James F. Plusquellic. 704-712
- Scan test sequencing hardware for structural testJamie Cullen. 713-720
- Tester retargetable patternsRohit Kapur, Thomas W. Williams. 721-727
- On RTL scan designYu Huang, Chien-Chung Tsai, Neelanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy. 728-737
- Enhanced reduced pin-count test for full-scan designHarald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier. 738-747
- OPMISR: the foundation for compressed ATPG vectorsCarl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko. 748-757
- March-based RAM diagnosis algorithms for stuck-at and coupling faultsJin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu. 758-767
- Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environmentJörg E. Vollrath, Randall Rooney. 768-775
- Bitline contacts in high density SRAMs: design for testability and stressabilityHerold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers. 776-782
- Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMsZaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter. 783-792
- Cost evaluation of coverage directed test generation for the IBM mainframeGilly Nativ, Steven Mittermaier, Shmuel Ur, Avi Ziv. 793-802
- : Identifying redundant gate replacements in verification by error modelingZeljko Zilic, Katarzyna Radecka. 803-812
- A validation fault model for timing-induced functional errorsQiushuang Zhang, Ian G. Harris. 813-820
- AMLETO: a multi-language environment for functional test generationAlessandro Fin, Franco Fummi, Graziano Pravadelli. 821-829
- Test evaluation and data on defect-oriented BIST architecture for high-speed PLLSeongwon Kim, Mani Soma. 830-837
- A high-resolution jitter measurement technique using ADC samplingSasikumar Cherubal, Abhijit Chatterjee. 838-847
- An approach to consistent jitter modeling for various jitter aspects and measurement methodsMasashi Shimanouchi. 848-857
- A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay lineAntonio H. Chan, Gordon W. Roberts. 858-867
- Low hardware overhead scan based 3-weight weighted random BISTSeongrnoon Wang. 868-877
- A new multiple weight set calculation algorithmHong Sik Kim, Jin-kyue Lee, Sungho Kang. 878-884
- Test vector encoding using partial LFSR reseedingC. V. Krishna, Abhijit Jas, Nur A. Touba. 885-893
- Two-dimensional test data compression for scan-based deterministic BISTHuaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich. 894-902
- Rapid-response temperature control provides new defect screening opportunitiesMark Malinoski, Burnell G. West. 903-907
- Optimal production test times through adaptive test programmingScott Benner, Oluseyi Boroffice. 908-915
- A new methodology for improved tester utilizationAjay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir. 916-923
- IS-FPGA : a new symmetric FPGA architecture with implicit scanMichel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian. 924-931
- BIST-based delay path testing in FPGA architecturesIan G. Harris, Premachandran R. Menon, Russell Tessier. 932-938
- On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systemsCecilia Metra, Andrea Pagano, Bruno Riccò. 939-947
- Moving from mixed signal to RF test hardware developmentJohn Ferrario, Randy Wolf, Hanyi Ding. 948-956
- A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipmentsHui S. Nam, Bernard Cuddy, Dieter Luecking. 957-964
- Testability implications in low-cost integrated radio transceivers: a Bluetooth case studyChristian Olgaard, Sule Ozev, Alex Orailoglu. 965-974
- Embedded DRAM built in self test and methodology for test insertionPeter Jakobsen, Jeffrey Dreibelbis, Gary Pomichter, Darren Anand, John E. Barth Jr., Michael R. Nelms, Jeffrey Leach, George M. Belansek. 975-984
- Shadow write and read for at-speed BIST of TDM SRAMsYuejian Wu, Liviu Calin. 985-994
- Memory built-in self-repair using redundant wordsVolker Schöber, Steffen Paul, Olivier Picot. 995-1001
- An effort-minimized logic BIST implementation methodXinli Gu, Sung Soo Chung, Frank Tsang, Jan Arild Tofte, Hamid Rahmanian. 1002-1010
- BIST and fault insertion re-use in telecom systemsSnezana Dikic, Lars-Johan Fritz, Dario Dell Aquia. 1011-1016
- Use of BIST in Sun Fire:::TM::: serversJohn Braden, Qing Lin, Brian Smith. 1017-1022
- Test wrapper and test access mechanism co-optimization for system-on-chipVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. 1023-1032
- Configuration free SoC interconnect BIST methodologyChauchin Su, Wenliang Tseng. 1033-1038
- Boolean and current detection of MOS transistor with gate oxide shortMichel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand. 1039-1048
- Testing for resistive opens and stuck opensChao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey. 1049-1058
- An evaluation of defect-oriented test: WELL-controlled low voltage testYasuo Sato, Msaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto. 1059-1067
- Fast test generation for circuits with RTL and gate-level viewsSrivaths Ravi, Niraj K. Jha. 1068-1077
- Combinational test generation for various classes of acyclic sequential circuitsYong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja. 1078-1087
- On static test compaction and test pattern ordering for scan designsXijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy. 1088-1097
- Tackling test trade-offs from design, manufacturing to market using economic modelingErik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff. 1098-1107
- A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assemblyThiagarajan Trichy, Peter Sandborn, Ravi Raghavan, Shubhada Sahasrabudhe. 1108-1117
- Unit level predicted yield: a method of identifying high defect density die at wafer sortRussell B. Miller, Walter C. Riordan. 1118-1127
- Pin electronics IC for high speed differential devicesAtsushi Oshima, John Poniatowski, Toshihiro Nomura. 1128-1133
- When zero picoseconds edge placement accuracy is not enoughJohn Cheng. 1134-1142
- Terabit-per-second automated digital testingDavid C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole. 1143-1189
- A stand-alone integrated test core for time and frequency domain measurementsMohamed Hafed, Nazmy Abaskharoun, Gordon W. Roberts. 1190-1199