Masashi Shimanouchi - researchr alias

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Viewing Publication 1 - 9 from 9

2016

SERDES external loopback test using production parametric-test hardwareShalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi. itc 2016: 1-7 [doi]

2013

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densitiesDaniel Chow, Masashi Shimanouchi, Mike Peng Li. itc 2013: 1-8 [doi]

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)Mike Peng Li, Masashi Shimanouchi, Hsinho Wu. cicc 2013: 1-8 [doi]

2009

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testingMasashi Shimanouchi, Mike P. Li, Daniel Chow. itc 2009: 1-8 [doi]

2004

Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATEMasashi Shimanouchi. itc 2003: 567-576 [doi]

Tester Architecture For The Source Synchronous BusA. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson. itc 2003: 738-747 [doi]

2003

Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in ProductionMasashi Shimanouchi. itc 2003: 48-57 [doi]

2002

New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device TestingMasashi Shimanouchi. itc 2002: 903-912 [doi]

2001

An approach to consistent jitter modeling for various jitter aspects and measurement methodsMasashi Shimanouchi. itc 2001: 848-857

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