Abstract is missing.
- Managing in the ATE Business - Postcards from the Past, Lessons for the FutureAlex d Arbeloff. 12 [doi]
- The Heisenberg Uncertainty of TestPeter C. Maxwell. 13 [doi]
- Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product LinesBozena Kaminska. 23 [doi]
- Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product LinesBill Bottoms. 24 [doi]
- Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product LinesGreg Spirakis. 25 [doi]
- Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product LinesDale E. Hoffman. 26 [doi]
- Testing The TesterRochit Rajsuman. 27 [doi]
- Testing the Tester: What Broke? Where? When? Why?Alfred L. Crouch. 28 [doi]
- Testing the Tester: Specification and Validation ApproachesJohn C. Johnson. 29 [doi]
- Testing The TesterRochit Rajsuman. 30 [doi]
- An Automated Methodology to Diagnose Geometric Defect in the EEPROM CellJean Michel Portal, L. Forli, Hassen Aziza, Didier Née. 31-36 [doi]
- Diagonal Test and Diagnostic Schemes for Flash MemorieSau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu. 37-46 [doi]
- Efficient Embedded Memory Testing with APGA. T. Sivaram, Daniel Fan, A. Yiin. 47-54 [doi]
- EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System ChipsBart Vermeulen, Tom Waayers, Sjaak Bakker. 55-63 [doi]
- Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip TestingPaul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. 64-73 [doi]
- Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing AlgorithmYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan. 74-82 [doi]
- On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large FanoutSudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita. 83-89 [doi]
- Parametric Failures in CMOS ICs - A Defect-Based AnalysisJaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins. 90-99 [doi]
- Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line TestingCecilia Metra, Stefano Di Francescantonio, T. M. Mak. 100-109 [doi]
- Frequency/Phase Movement Analy i by Orthogonal DemodulationHideo Okawara. 110-119 [doi]
- A Wavelet-Based Timing Parameter Extraction MethodMani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina. 120-128 [doi]
- An Embedded Core for Sub-Picosecond Timing MeasurementsSassan Tabatabaei, André Ivanov. 129-137 [doi]
- Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data VolumeM. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor. 138-147 [doi]
- Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture TechniqueVishal Jain, John A. Waicukauski. 148-153 [doi]
- Packet-Based Input Test Data Compression TechniquesErik H. Volkerink, Ajay Khoche, Subhasish Mitra. 154-163 [doi]
- DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMsO. Hirabayashi, A. Suzuki, T. Yabe, A. Kawasumi, Y. Takeyama, K. Kushida, A. Tohata, N. Otsuka. 164-169 [doi]
- A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer TestShigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo. 170-177 [doi]
- On-Chip Repair and an ATE Independent Fusing MethodologyBruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater. 178-186 [doi]
- Integration of SRAM Redundancy into Production TestJayasanker Jayabalan, Juraj Povazanec. 187-193 [doi]
- Verifying Properties Using Sequential ATPGJacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab. 194-202 [doi]
- Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array SystemsGanapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir. 203-212 [doi]
- Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic CircuitsJayanta Bhadra, Narayanan Krishnamurthy. 213-222 [doi]
- Design Rewiring Using ATPGAndreas G. Veneris, Magdy S. Abadir, Mandana Amiri. 223-232 [doi]
- Fault Tuples in Diagnosis of Deep-Submicron CircuitsRonald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels. 233-241 [doi]
- A Persistent Diagnostic Technique for Unstable DefectsYasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura. 242-249 [doi]
- Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault DiagnosisDavid B. Lavo, Ismed Hartanto, Tracy Larrabee. 250-259 [doi]
- An Effective Diagnosis Method to Support Yield ImprovementCamelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg. 260-269 [doi]
- Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test DevelopmentTom Austin, Charisma Canlas, Brady Morgan, Jorge Luis Rodriguez. 270-279 [doi]
- DUT Capture Using Simultaneous Logic AcquisitionA. T. Sivaram, William Fritzsche, Toshitaka Koshi, Nam Lai. 280-289 [doi]
- Considerations for STIL Data ApplicationGregory A. Maston. 290-296 [doi]
- Verification of Device Interface Hardware Interconnections Prior to the Start of TestingGuy Peterson. 297-300 [doi]
- Embedded Deterministic Test for Low-Cost Manufacturing TestJanusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian. 301-310 [doi]
- X-Compact: An Efficient Response Compaction Technique for Test Cost ReductionSubhasish Mitra, Kee Sup Kim. 311-320 [doi]
- Reducing Test Dat Volume Using LFSR Reseeding with Seed CompressionC. V. Krishna, Nur A. Touba. 321-330 [doi]
- Multiscan-Based Test Compression and Hardware Decompression Using LZ77Francis G. Wolff, Christos A. Papachristou. 331-339 [doi]
- Embedded Memory Test and Repair: Infrastructure IP for SOC YieldYervant Zorian. 340-349 [doi]
- An Integrated Approach to Yield Loss CharacterizationMark Craig, Alvin Jee, Prashant Maniar. 350-356 [doi]
- Robustness IPs for Reliability and Security of SoCsEric Dupont, Michael Nicolaidis. 357-364 [doi]
- XIDEN: Crosstalk Target Identification FrameworkShahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer. 365-374 [doi]
- Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit InterconnectsAditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal. 375-383 [doi]
- Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing AnalysisBipul Chandra Paul, Kaushik Roy. 384-390 [doi]
- A New Algorithm for Global Fault Collapsing into Equivalence and Dominance SetsA. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre. 391-397 [doi]
- On Testing High-Performance Custom Circuits without Explicit Testing of the Internal FaultsLi-C. Wang, Magdy S. Abadir, Juhong Zhu. 398-406 [doi]
- Analysis of Delay Test Effectiveness with a Multiple-Clock SchemeJing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams. 407-416 [doi]
- Realistic Spring Probe Testing Methods and ResultsD. Gessel, A. Slcoum, A. Sprunt, S. Ziegenhagen. 417-423 [doi]
- Low-Contact-Force Probing on Copper ElectrodesKenichi Kataoka, Toshihiro Itoh, Katsuya Okumura, Tadatomo Suga. 424-429 [doi]
- Compensation of Transmission Line Loss for Gbit/s Test on ATEsWolfram Humann. 430-437 [doi]
- Multi-Purpose Digital Test Core Utilizing Programmable LogicJ. S. Davis, David C. Keezer. 438-445 [doi]
- Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing CostStephen K. Sunter, Benoit Nadeau-Dostie. 446-455 [doi]
- Realizing the Benefits of Structural Test for Intel MicroprocessorsMike Mayberry, John Johnson, Navid Shahriari, Mike Tripp. 456-463 [doi]
- Isolating and Removing Sources of Variation in Test DataDavid Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge. 464-471 [doi]
- A Multi-Language Goal-Tree Based Functional Test Planning SystemRajneesh Mahajan, Ramesh Govindarajulu, J. R. Armstrong, F. G. Gray. 472-481 [doi]
- System Manufacturing Test Cost ModelDavid Williams, Anthony P. Ambler. 482-490 [doi]
- On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-ChipsYi Zhao, Li Chen, Sujit Dey. 491-499 [doi]
- Static Analysis of SEU Effects on Software ApplicationsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 500-508 [doi]
- Experimental Evaluation of Scan Tests for BridgesSreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah. 509-518 [doi]
- A Set of Benchmarks fo Modular Testing of SOCsErik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty. 519-528 [doi]
- Effective and Efficient Test Architecture Design for SOCsSandeep Kumar Goel, Erik Jan Marinissen. 529-538 [doi]
- On the Use of k-tuples for SoC Test Schedule RepresentationSandeep Koranne, Vikram Iyengar. 539-548 [doi]
- Physical Principles of Interface DesignTodd Sargent. 549-554 [doi]
- What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit RegionThomas P. Warwick. 555-564 [doi]
- The Process and Challenges of a High-Speed DUT Board ProjectDavid E. McFeely. 565-573 [doi]
- Test Methodology for Motorola s High Performance e500 Core Based on PowerPC Instruction Set ArchitectureB. Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina. 574-583 [doi]
- Support for Debugging in the Alpha 21364 MicroprocessorTimothe Litt. 584-589 [doi]
- FRITS - A Microprocessor Functional BIST MethodPraveen Parvathala, Kaila Maneparambil, William Lindsay. 590-598 [doi]
- FPGA Test and CoverageShahin Toutounchi, Andrew Lai. 599-607 [doi]
- Fault Grading FPGA Interconnect Test ConfigurationsMehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey. 608-617 [doi]
- BIST-Based Diagnosis of FPGA InterconnectCharles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici. 618-627 [doi]
- Facilitating Rapid First Silicon DebugHari Balachandran, Kenneth M. Butler, Neil Simpson. 628-637 [doi]
- Core-Based Scan Architecture for Silicon DebugBart Vermeulen, Tom Waayers, Sandeep Kumar Goel. 638-647 [doi]
- Re-Using DFT Logic for Functional and Silicon Debugging TestXinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung. 648-656 [doi]
- The Manic Depression of Microprocessor DebugDon Douglas Josephson. 657-663 [doi]
- Silicon Symptoms to Solutions: Applying Design for Debug TechniquesCarol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger. 664-672 [doi]
- Screening MinVDD Outliers Using Feed-Forward Voltage TestingRobert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner. 673-682 [doi]
- Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data EvaluationMinh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O Neill. 683-692 [doi]
- Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability ModelThomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh. 693-699 [doi]
- Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of JitterY. Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, R. D. Brink. 700-709 [doi]
- On the Accuracy of Jitter Separation from Bit Error Rate FunctionMike P. Li, Jan B. Wilstrup. 710-716 [doi]
- A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal JitterTakahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie. 717-725 [doi]
- A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-ProcessorsIshwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D Souza, Amitava Majumdar. 726-735 [doi]
- Optimal BIST Using an Embedded MicroprocessorSungbae Hwang, Jacob A. Abraham. 736-745 [doi]
- An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance ImprovementsDave Stang, Ramaswami Dandapani. 746-754 [doi]
- A Structured Graphical Tool for Analyzing Boundary Scan ViolationsMichael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora. 755-762 [doi]
- Improved Digital I/O Ports Enhance Testability of InterconnectionsAdam Kristof. 763-772 [doi]
- Testing Finite State Machines Based on a Structural Coverage Metric Sezer Gören, F. Joel Ferguson. 773-780 [doi]
- An Efficient Linear Time Algorithm for Scan Chain Optimization and RepartitioningDavid Berthelot, Samit Chaudhuri, Hamid Savoj. 781-787 [doi]
- Integrating DFT in the Physical Synthesis FlowLoïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur. 788-795 [doi]
- Power Driven Chaining of Flip-Flops in Scan ArchitecturesYannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. 796-803 [doi]
- Automatic Scan Insertion and Test Generation for Asynchronous CircuitsFrank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff. 804-813 [doi]
- RTL Level Preparation of High-Quality/Low-Energy/Low-Power BISTMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras. 814-823 [doi]
- An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future ProcessesZhigang Jiang, Sandeep K. Gupta. 824-833 [doi]
- Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BISTSeongmoon Wang. 834-843 [doi]
- Scan Power Reduction Through Test Data Transition Frequency AnalysisOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu. 844-850 [doi]
- Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCsCarsten Wegener, Michael Peter Kennedy. 851-860 [doi]
- A New Test Generation Approach for Embedded Analogue Cores in SoCM. Stancic, L. Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff. 861-869 [doi]
- Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial RequirementsGunter Krampl, Marco Rona, Hermann Tauber. 870-878 [doi]
- Use of Pipeline Converters for ATE ApplicationsMaurizio Gavardoni. 879-884 [doi]
- R4X/D4X - Formatters for Flexible Test System ArchitectureAhmed Rashid Syed. 885-893 [doi]
- CMOS Circuit Technology for Precise GHz Timing GeneratorToshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto. 894-902 [doi]
- New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device TestingMasashi Shimanouchi. 903-912 [doi]
- High Current DPS Architecture for Sort Test ChallengeJean-Pascal Mallet. 913-922 [doi]
- A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan ArchitecturTapan J. Chakraborty, Chen-Huan Chiang. 923-929 [doi]
- Efficient Design of System Test: A Layered ArchitectureAndrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei. 930-939 [doi]
- Itelligent Agents and BIST/BISR - Working Together in Distributed SystemsLiviu Miclea, Szilárd Enyedi, Alfredo Benso. 940-946 [doi]
- Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMsB. Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura. 947-953 [doi]
- Improved IDDQ Testing with Empirical Linear PredictionDavid I. Bergman, Hans Engler. 954-963 [doi]
- Comparison of IDDQ Testing and Very-Low Voltage TestingBram Kruseman, Stefan van den Oetelaar, Josep Rius. 964-973 [doi]
- Finding a Small Set of Longest Testable Paths that Cover Every GateManish Sharma, Janak H. Patel. 974-982 [doi]
- Techniques to Reduce Data Volume and Application Time for Transition TestXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran. 983-992 [doi]
- On Identifying Indistinguishable Path Delay Faults and Improving DiagnosisRamesh C. Tekumalla, Scott Davidson. 993-1002 [doi]
- Application of High-Quality Built-In Test to Industrial DesignsKazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo. 1003-1012 [doi]
- Pseudo Random Patterns Using Markov Sources for Scan BISTNadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz. 1013-1021 [doi]
- Test and Evaluation of Multiple Embedded Mixed-Signal Test CoresMohamed Hafed, Gordon W. Roberts. 1022-1030 [doi]
- High Accuracy Stimulus Generation for A/D Converter BISTAubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello. 1031-1039 [doi]
- valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test CulpritsJohn Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns. 1040-1049 [doi]
- Wafer/Package Test Mix for Optimal Defect DetectionPeter C. Maxwell. 1050-1055 [doi]
- IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital NetworksBill Eklow, Carl Barnhart, Kenneth P. Parker. 1056-1065 [doi]
- Test Coverage: What Does It Mean When a Board Test Passes?Kathy Hird, Kenneth P. Parker, Bill Follis. 1066-1074 [doi]
- Built-In Self Test of CMOS-MEMS AccelerometersNilmoni Deb, R. D. (Shawn) Blanton. 1075-1084 [doi]
- Incremental Diagnosis of Multiple Open-InterconnectsJiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi. 1085-1092 [doi]
- Signal Integrity Loss in SoC s Interconnects: A Diagnosis Approach Using Embedded MicroprocessorMohammad H. Tehranipour, Mehrdad Nourani. 1093-1102 [doi]
- Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System ChipsSandeep Kumar Goel, Bart Vermeulen. 1103-1110 [doi]
- Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead. 1111-1119 [doi]
- Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech. 1120-1129 [doi]
- A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital CircuitsBhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi. 1130-1139 [doi]
- WCDMA Testing with a Baseband/IF Range AWGKoji Asami, Yasuo Furukawa, Michael Purtell, Motoo Ueda, Karl Watanabe, Toshifumi Watanabe. 1140-1145 [doi]
- Testing Wireless Local Area Network Transceiver ICs at 5 GHzKevin M. MacKay. 1146-1150 [doi]
- Architecting Millisecond Test Solutions for Wireless Phone RFIC sJohn Ferrario, Randy Wolf, Steve Moss. 1151-1158 [doi]
- Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth ConstraintsVikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty. 1159-1168 [doi]
- Adapting an SoC to ATE Concurrent Test CapabilitiesRainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer. 1169-1175 [doi]
- Dedicated Autonomous Scan-Based Testing (DAST) for Embedded CoresMohsen Nahvi, André Ivanov, Resve A. Saleh. 1176-1184 [doi]
- Test Coverage Models for System Test?David Williams. 1185 [doi]
- Can IC Test Learn from How a Tester is TestedRochit Rajsuman. 1186 [doi]
- What Can IC Test Teach System Test?Scott Davidson. 1187 [doi]
- Is It Rocket Science?Anthony P. Ambler. 1188-1189 [doi]
- TAPS All Over My Chips! So Now What Do I Do?Bart Vermeulen. 1190 [doi]
- Inevitable Use of TAP Domains in SOCsLee Whetsel. 1191 [doi]
- TAPs All Over My ChipsSteven F. Oakland. 1192 [doi]
- TAPS All Over My ChipsTeresa L. McLaurin. 1193-1194 [doi]
- Good Scan = Good Quality Level? Well, It Depends ?Anjali Kinra Vij. 1195 [doi]
- Scan and BIST Can Almost Achieve Test Quality LevelsCarol Pyron. 1196 [doi]
- Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without ItGrady Giles. 1197 [doi]
- Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer ProductsPhil Nigh. 1198 [doi]
- Trouble With ScanDavid M. Wu. 1199-1200 [doi]
- A/MS BISTs: The FACTS, Just the FactsArnold Frisch. 1201 [doi]
- Mixed-Signal BIST: Fact or FictionKarim Arabi. 1202 [doi]
- Mixed Signal BIST: Fact or FictionLee Y. Song. 1203 [doi]
- Mixed-Signal BIST: Fact or FictionGordon W. Roberts. 1204 [doi]
- IC Mixed-Signal BIST: Separating Facts from FictionStephen K. Sunter. 1205 [doi]
- Mission Impossible? Open Architecture ATEDennis R. Conti. 1207 [doi]
- Mission Possible? Open Architecture ATEPaul F. Scrivens. 1208 [doi]
- Is an Open Architecture Tester Really Achievable?Paul D. Roddy. 1209 [doi]
- The Consequences of an Open ATE ArchitectureSergio M. Perez. 1210 [doi]
- An Open Architecture for Semiconductor Test: Enablers and ChallengesMark Jagiela. 1211 [doi]
- Open ATE Architecture: Key ChallengesBurnell G. West. 1212-1213 [doi]
- The Role of Test in a Highly Outsourced Business ModelBill Price. 1214 [doi]
- The Yield of Test OutsourcingDavide Appello. 1215 [doi]
- The Impact of Outsourcing on TestFidel Muradali. 1216 [doi]
- Outsourcing Test without Standards?Peter Muhmenthaler. 1217-1218 [doi]
- Test and Repair of Embedded Flash MemoriesJean Michel Daga. 1219 [doi]
- Test Time Impact of Redundancy Repair in Embedded Flash MemoryPaul Okino. 1220 [doi]
- Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory)Riichiro Shirota. 1221 [doi]
- Selective Optimization of Test for Embedded Flash MemoryRoger Barth. 1222 [doi]
- Test and Repair of Nonvolatile Commodity and Embedded MemoriesShigeo Tsuchida. 1223-1224 [doi]
- Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge?Mustapha Slamani. 1225 [doi]
- Wireless SOC Testing: Can RF Testing Costs Be Reduced?Alan Kafton. 1226-1227 [doi]
- Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge?C. Hawkins, J. Segura. 1228 [doi]
- Wireless SOC Testing: Can RF Testing Costs Be Reduced?Takahiro J. Yamaguchi. 1229 [doi]
- GHz Testing and Its Fuzzy TargetsDavid C. Keezer. 1230 [doi]
- Multi-GHz Interface Devices Should Be Tested Using External Test ResourcesManoj Sachdev. 1231 [doi]
- Challenges and Solutions for Multi-Gigahertz Testing Mike Tripp. 1232 [doi]
- Multi-Gigahertz Digital Test Challenges and TechniquesUlrich Schoettmer. 1233-1234 [doi]
- Is Board Test Worth Talking About?Bill Eklow. 1235 [doi]
- Board Test: Wanted Dead or AliveGordon D. Robinson. 1236 [doi]
- Is ITC Bored with Board Test?Kenneth M. Butler. 1237 [doi]
- Board Test Is NOT MatureKenneth P. Parker. 1238 [doi]
- Panel: Board Test and ITC: What Does the Future Hold? Monica Lobetti Bodoni. 1239 [doi]
- Neighbor Selection for Variance Reduction in IDDQ and Other Parametric DataW. Robert Daasch, Kevin Cota, James McNames, Robert Madge. 1240 [doi]