Chen-Huan Chiang - researchr alias

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Viewing Publication 1 - 15 from 15

2011

Design for Bit Error Rate estimation of high speed serial linksUjjwal Guin, Chen-Huan Chiang. vts 2011: 278-283 [doi]

2010

A Common Language Framework for Next-Generation Embedded TestingMichele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook. dt, 27(5):36-49, 2010. [doi]

2008

A New Language Approach for IJTAGMichele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook. itc 2008: 1-10 [doi]

Problems Using Boundary-Scan for Memory Cluster TestsBradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker. itc 2008: 1-10 [doi]

2007

A practical approach to comprehensive system test & debug using boundary scan based test architectureTapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren. itc 2007: 1-10 [doi]

FPGA Prototyping of a Scan Based System-On-Chip DesignBrendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook. recosoc 2007: 121-126

2004

Testing and Remote Field Update of Distributed Base Stations in a Wireless NetworkChen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung. itc 2003: 711-718 [doi]

2002

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan ArchitecturTapan J. Chakraborty, Chen-Huan Chiang. itc 2002: 923-929 [doi]

2000

End-to-end testing for boards and systems using boundary scanRobert W. Barr, Chen-Huan Chiang, Edward L. Wallace. itc 2000: 585-592

BIST TPG for Combinational Cluster Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. et, 16(5):427-442, 2000. [doi]

BIST TPG for SRAM cluster interconnect testing at board levelChen-Huan Chiang, Sandeep K. Gupta. ats 2000: 58-65 [doi]

1998

BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. ats 1998: 244-252 [doi]

1997

BIST TPG for faults in system backplanesChen-Huan Chiang, Sandeep K. Gupta. iccad 1997: 406-413 [doi]

BIST TPGs for Faults in Board Level Interconnect via Boundary ScanChen-Huan Chiang, Sandeep K. Gupta. vts 1997: 376-383 [doi]

1994

Random pattern testable logic synthesisChen-Huan Chiang, Sandeep K. Gupta. iccad 1994: 125-128 [doi]

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