Table of Contents

• The New Frontier for Testing: Nano Meter TechnologiesT. Williams. 2 [doi]
• BIST Diagnostics, Part 1: Simulation ModelsJacob Savir. 8-14 [doi]
• Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a CircuitFrank Mayer, Albrecht P. Stroele. 15-20 [doi]
• Test Cycle Count Reduction in a Parallel Scan BIST EnvironmentBechir Ayari, Prab Varma. 21-26 [doi]
• A BIST Scheme for Asynchronous LogicVladimir Castro Alves, Felipe M. G. França, Edson do Prado Granja. 27-32 [doi]
• A Methodology for Minimum Area Cellular Automata GenerationPaulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Wang Jiang Chau. 33 [doi]
• A High-Level Synthesis Method for Weakly Testable Data PathsMichiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara. 40-45 [doi]
• Alleviating DFT Cost Using Testability Driven HLSMarie-Lise Flottes, R. Pires, Bruno Rouzeyre. 46-51 [doi]
• Optimizing HW/SW Codesign towards Reliability for Critical-Application SystemsFabian Vargas, E. Bezerra, L. Wulff, Daniel Barros Jr.. 52-57 [doi]
• An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy IdentificationHideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita. 58-63 [doi]
• Economical Importance of the Maximum Chip AreaJunichi Hirase. 64 [doi]
• A Probabilistic Model for Path Delay FaultsCheng-Wen Wu, Chih-Yuang Su. 70-75 [doi]
• A New Low-Cost Method for Identifying Untestable Path Delay FaultsZhongcheng Li, Yinghua Min, Robert K. Brayton. 76-81 [doi]
• False-Path Removal Using Delay Fault SimulationMarwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell. 82-87 [doi]
• An Automatic Test Pattern Generator for At-Speed Robust Path Delay TestingYuan-Chieh Hsu, Sandeep K. Gupta. 88-95 [doi]
• Delay Testing with Double ObservationsHuawei Li, Zhongcheng Li, Yinghua Min. 96 [doi]
• On a Logical Fault Model H1SGLF for Enhancing Defect CoverageJunzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi. 102-107 [doi]
• Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault SimulationHiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu. 108-112 [doi]
• On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault SimulationKuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh. 113-118 [doi]
• Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic CircuitsS. M. Aziz, Joarder Kamruzzaman. 119 [doi]
• Rough-Hierarchical Testing for Safety Critical SoftwareHaiying Tu, Fangmei Wu, Xiaoxu Ren. 126-130 [doi]
• A Structured Testing Approach for DSP SoftwareEric Mouchel La Fosse. 131 [doi]
• IDDQ Test Methodology and Tradeoffs for Scan/Non-Scan DesignsMukund R. Patel, Julian Fierro, Steve Pico. 138-143 [doi]
• Design for Diagnosability of CMOS CircuitsXiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita. 144-149 [doi]
• IDDQ Defect Detection in Deep Submicron CMOS ICsSandip Kundu. 150-152 [doi]
• ATE Features for IDDQ TestingMark G. Faust. 153 [doi]
• A New Technique to Ensure Quality of Test PatternsPeng-Cheng Koo, San-Liek Pang. 160-164 [doi]
• Testing CPU Based Boards for Functionality Using Bus Cycle Signature SystemS. R. Sabapathi. 165-171 [doi]
• Non-Intrusive Testing of High-Speed CML CircuitsVikram Devdas, André Ivanov. 172-178 [doi]
• Fast Window Test Method of Hysteresis TestTerry Corpuz. 179-183 [doi]
• Development of a Multi-Channel PC-Based Hard Disk Drive Bode-Plot GeneratorKin Wee Choo, Guoxiao Guo, Ben M. Chen. 184 [doi]
• An Optimal Time Expansion Model Based on Combinational ATPG for RT level CircuitsTomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara. 190-197 [doi]
• Static Test Compaction for Scan-Based Designs to Reduce Test Application TimeIrith Pomeranz, Sudhakar M. Reddy. 198-203 [doi]
• A Non-Scan DFT Method for Controllers to Achieve Complete Fault EfficiencySatoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara. 204-211 [doi]
• Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict DetectionJ. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor. 212 [doi]
• On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic GatesTeruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa. 222-227 [doi]
• Testing for Floating Gates Defects in CMOS CircuitsSumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell. 228-236 [doi]
• Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized PathsNobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu. 237 [doi]
• BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. 244-252 [doi]
• Fault Detection in a Tristate System EnvironmentWenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi. 253-258 [doi]
• Comprehensive Interconnect BIST Methodology for Virtual Socket InterfaceChauchin Su, Yue-Tsung Chen. 259 [doi]
• SRAM-Based FPGA s: Testing the Interconnect/Logic InterfaceMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 266-271 [doi]
• Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGANoriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita. 272-277 [doi]
• A Diagnosis Method for Interconnects in SRAM Based FPGAsYinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi. 278-282 [doi]
• Testing and Diagnosis of Interconnect Structures in FPGAsSying-Jyan Wang, Chao-Neng Huang. 283 [doi]
• An Approach to the On-Line Testing of Operational AmplifiersJaime Velasco-Medina, Marcelo Lubaszewski, Michael Nicolaidis. 290-295 [doi]
• Self-Dual Duplication for Error DetectionVl. V. Saposhnikov, V. V. Saposhnikov, Alexej Dmitriev, Michael Gössel. 296-300 [doi]
• On-Line Error Detection Schemes for a Systolic Finite-Field InverterYu-Chun Chuang, Cheng-Wen Wu. 301-305 [doi]
• Fault Tolerance of a Tree-Connected Multiprocessor System and its Arraylike LayoutSumito Nakano, Naotake Kamiura, Yutaka Hata. 306 [doi]
• Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential CircuitsYoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita. 312-317 [doi]
• An Off-Chip Current Sensor for IDDQ Testing of CMOS ICsMd. Altaf-Ul-Amin, Zahari Mohamed Darus. 318-322 [doi]
• Integrated Current Sensing Device for Micro IDDQ TestKoichi Nose, Takayasu Sakurai. 323-326 [doi]
• A High-Speed IDDQ Sensor for Low-Voltage ICsMasaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita. 327 [doi]
• Power Analysis of DRAMsJörg E. Vollrath, Markus Huebl, Ernst Stahl. 334-339 [doi]
• Consequences of Port Restriction on Testing Address Decoders in Two-Port MemoriesSaid Hamdioui, A. J. van de Goor. 340-347 [doi]
• Dynamic Power Supply Current Testing of SRAMsJian Liu, Rafic Z. Makki, Ayman I. Kayssi. 348-353 [doi]
• March PS(23N) Test for DRAM Pattern-Sensitive FaultsVyacheslav N. Yarmolik, Yuri V. Klimets, Serge N. Demidenko. 354 [doi]
• Dynamic Test Set Generation for Analog Circuits and SystemsSam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang. 360-365 [doi]
• DC Nonlinear Circuit Fault Simulation With Large Change SensitivityMike W. T. Wong, Matthew Worsman. 366-371 [doi]
• BISTing Switched-Current CircuitsMichel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand. 372-377 [doi]
• Analog Module Metrology Using MNABST-1 P1149.4 Test ChipY. T. Chen, C. Su. 378-382 [doi]
• A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOsFlorence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand. 383-387 [doi]
• Theory and Application of Multiple Attractor Cellular Automata for Fault DiagnosisKolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri. 388 [doi]
• Formal Design Techniques - Theory and Engineering RealityChryssa Dislis, Gerry Musgrave, Roger B. Hughes. 394-398 [doi]
• Verification of Asynchronous Circuits with Bounded Inertial Gate DelaysJ. Gong, Eddie M. C. Wong. 399-401 [doi]
• Verification Pattern Generation for Core-Based Design Using Port Order Fault ModelShing-Wu Tung, Jing-Yang Jou. 402-407 [doi]
• Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication ProtocolsShin ichi Nagano, Hiroyuki Fujita, Yoshiaki Kakuda, Tohru Kikuno. 408-412 [doi]
• Design and Simulation of a RISC-Based 32-bit Embedded On-Board ComputerZhen Guo, He Li, Shuling Guo, Dongsheng Wang. 413 [doi]
• A Ring Architecture Strategy for BIST Test Pattern GenerationChristophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault. 418-423 [doi]
• Exploiting BIST Approach for Two-Pattern TestingXiaowei Li, Paul Y. S. Cheung. 424-429 [doi]
• Evaluating BIST Architectures for Low PowerC. P. Ravikumar, N. Satya Prasad. 430-434 [doi]
• A BIST Structure to Test Delay Faults in a Scan EnvironmentPatrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel. 435-439 [doi]
• An Examination of PRPG Selection Approaches for Large, Industrial DesignsIsmet Bayraktaroglu, K. Udawatta, Alex Orailoglu. 440 [doi]
• Test Generation for Synchronous Sequential Circuits to Reduce Storage RequirementsIrith Pomeranz, Sudhakar M. Reddy. 446-451 [doi]
• Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential CircuitsMichael S. Hsiao, Srimat T. Chakradhar. 452-457 [doi]
• Vector Restoration Using Accelerated Validation and RefinementSurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy. 458-466 [doi]
• On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy. 467-471 [doi]
• Synthesis of Sequential Circuits with Clock Control to Improve TestabilityKent L. Einspahr, Shashank K. Mehta, Sharad C. Seth. 472 [doi]
• A Test Pattern Generation Algorithm Exploiting Behavioral InformationSilvia Chiusano, Fulvio Corno, Paolo Prinetto. 480-485 [doi]
• A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test EliminationIrith Pomeranz, W. Kent Fuchs. 486-491 [doi]
• Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BISTMadhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich. 492-499 [doi]
• Test Pattern Generation for Column Compression MultiplierPingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng. 500-503 [doi]
• An Efficient Random-like TestingShiyi Xu, Jianhua Gao. 504 [doi]
• Microsystem Testing: Challenge or Common Knowledge?Hans G. Kerkhoff. 510-511 [doi]
• Microsystems Testing: A ChallengeMichel Renovell. 512 [doi]
• Bridging the Gap between Microelectronics and Micromechanics TestingMarcelo Lubaszewski. 513 [doi]
• Testing Embedded Memories: Is BIST the Ultimate Solution?Cheng-Wen Wu. 516-517 [doi]
• An ASIC Designer s Point of ViewMarcel Jacomet. 518 [doi]
• Testing of Embedded Memories - The AggregateRafic Z. Makki. 519 [doi]
• Answers to the Key IssuesA. J. van de Goor. 520 [doi]
• A DFT Methodology for High-Speed MCM Based on Boundary-Scan TechniquesYasunori Sameshima, Tomoo Fukazawa. 521 [doi]