Koichi Nose - researchr alias

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Viewing Publication 1 - 26 from 26

2024

20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot ApplicationsKoichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi. isscc 2024: 364-366 [doi]

2019

2Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose. vlsic 2019: 248 [doi]

2015

Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommitteeJan Genoe, Koichi Nose. isscc 2015: 288-289 [doi]

F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levelsMarian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose. isscc 2015: 1-2 [doi]

2012

2010

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effectEisuke Saneyoshi, Koichi Nose, Masayuki Mizuno. isscc 2010: 192-193 [doi]

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level TestingYoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda. jssc, 45(10):2057-2065, 2010. [doi]

2009

2008

2007

LAGS System Using Data/Instruction Grain Power ControlMakoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada. isscc 2007: 66-587 [doi]

Fine-Grain Redundant Logic Using Defect-Prediction Flip-FlopsToru Nakura, Koichi Nose, Masayuki Mizuno. isscc 2007: 402-611 [doi]

2006

2004

Frequency-hopping vernier clock generators for multiple clock domain SoCsHiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka. cicc 2004: 91-94 [doi]

2002

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technologyKoichi Nose, Takayasu Sakurai. islped 2002: 24-29 [doi]

V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processorsKoichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai. jssc, 37(3):413-419, 2002. [doi]

2001

Design methodology and optimization strategy for dual-VTH scheme using commercially available toolsMasayuki Hirabayashi, Koichi Nose, Takayasu Sakurai. islped 2001: 283-286 [doi]

TH-hopping scheme for 82% power saving in low-voltage processorsKoichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai. cicc 2001: 93-96 [doi]

2000

1998

Integrated Current Sensing Device for Micro IDDQ TestKoichi Nose, Takayasu Sakurai. ats 1998: 323-326 [doi]

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