Abstract is missing.
- A robust large signal non-quasi-static MOSFET model for circuit simulationHailing Wang, Gennady Gildenblat. 5-8 [doi]
- RF distortion analysis with compact MOSFET modelsPeter Bendix, Pat Rakers, P. Wagh, Laurent Lemaitre, W. Grabinski, Colin C. McAndrew, X. Gu, Gennady Gildenblat. 9-12 [doi]
- The next generation BSIM for sub-100nm mixed-signal circuit simulationXuemei Xi, Jin He, Mohan V. Dunga, Chung-Hsun Lin, Babak Heydari, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu. 13-16 [doi]
- Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuitsHamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy. 17-20 [doi]
- A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasisPaul Westergaard, Timothy O. Dickson, Sorin P. Voinigescu. 23-26 [doi]
- 10+ Gb/s 90nm CMOS serial link demo in CBGA packageSergey V. Rylov, Scott K. Reynolds, Daniel Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna. 27-30 [doi]
- A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalizationVishnu Balan, Joe Caroselli, Jenn-Gang Chern, Chintan Desai, Cathy Liu. 31-34 [doi]
- A low power capacitive coupled bus interface based on pulsed signalingJongsun Kim, Jung Hwan Choi, Changhyun Kim, A. F. Chang, Ingrid Verbauwhede. 35-38 [doi]
- A 10Gb/s data-dependent jitter equalizerJames Buckwalter, Ali Hajimiri. 39-42 [doi]
- A 0.8V accurately-tuned continuous-time filterGowtham Vemulapalli, Pavan Kumar Hanumolu, Un-Ku Moon. 45-48 [doi]
- A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver [mobile phone applications]Brian Guthrie, Tony Sayers, Adrian Spencer, John Hughes. 49-52 [doi]
- rd-order Chebyshev low pass filterYoung-Ho Kim, Jung Woo Park, Mun-Yang Park, Hyun-Kyu Yu. 53-56 [doi]
- th order lowpass filter with class AB CMFB in 0.35 μm CMOS technologyPankaj Pandey, José Silva-Martínez, Xuemei Liu. 57-60 [doi]
- Cellular handset integration - SIP vs. SOCWilliam Krenik, Dennis Buss, Peter Rickert. 63-70 [doi]
- MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devicesCynthia Trigas, Stefan Doll, Joachim Kruecken. 71-79 [doi]
- 2 radio and CPU/DSP/RAM/ROMGiuseppe Gramegna, Massimo Franciotta, Valentina Mandara, Nino G. Bellantone, Michele Vaiana, Mario Paporo, Marco Losi, Sabyasachi Das, Philip G. Mattos. 81-84 [doi]
- Observation of one-fifth-of-a-clock wake-up time of power-gated circuitTakayuki Miyazaki, Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai. 87-90 [doi]
- Frequency-hopping vernier clock generators for multiple clock domain SoCsHiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka. 91-94 [doi]
- Device sizing for minimum energy operation in subthreshold circuitsBenton H. Calhoun, Alice Wang, Anantha Chandrakasan. 95-98 [doi]
- Cross talk countermeasures in inductive inter-chip wireless superconnectNoriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda. 99-102 [doi]
- A breakdown voltage doubler for high voltage swing driversSam Mandegaran, Ali Hajimiri. 103-106 [doi]
- An overview of automated macromodelling techniques for mixed-signal systemsJaijeet Roychowdhury. 109-116 [doi]
- Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptionsNing Dong, Jaijeet Roychowdhury. 117-120 [doi]
- Fast, accurate prediction of PLL jitter induced by power grid noiseXiaolue Lai, Jaijeet Roychowdhury. 121-124 [doi]
- A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulationYutao Hu, Kartikeya Mayaram. 125-128 [doi]
- An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiersShingo Yamanouchi, Kazuaki Kunihiro, Hikaru Hida. 129-132 [doi]
- Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortionVincent W. Leung, Junxiong Deng, Prasad S. Gudem, Lawrence E. Larson. 133-136 [doi]
- A 250MHz-2GHz wide range delay-locked loopByung-Guk Kim, Lee-Sup Kim. 139-142 [doi]
- A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRsAbdulkerim L. Coban, Mustafa H. Koroglu, Kashif A. Ahmed. 143-146 [doi]
- Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]A. Maxim. 147-150 [doi]
- An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitterStephen Williams, Hugh Thompson, Mike Hufford, Eric Naviasky. 151-154 [doi]
- A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial dataChih-Wei Yao, Hiep T. Pham, Alan N. Willson Jr.. 155-158 [doi]
- A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 μm CMOSJonne Lindeberg, Jouko Vankka, Johan Sommarek, Kari Halonen. 159-162 [doi]
- High-speed direct digital frequency synthesizers in 0.25-μm CMOSAntonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra. 163-166 [doi]
- A 250 mW class D design with direct battery hookup in a 90 nm process [audio band switching amplifier]Brett Forejt, Vijay Rentala, Gangadhar Burra, Jose Arteaga. 169-172 [doi]
- A class-D amplifier using a spectrum shaping technique [audio power amplifier]Akira Yasuda, Takashi Kimura, Koichiro Ochiai, Toshihiko Hamasaki. 173-176 [doi]
- A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]Pascal Lo Ré, Yoshihisa Fujimoto, Hitoshi Tani, Masayuki Miyamoto. 177-180 [doi]
- Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresisSotir Ouzounov, Engel Roza, Hans Hegt, Gerard Van der Weide, Arthur H. M. van Roermund. 181-184 [doi]
- A study of error sources in current steering digital-to-analog convertersDouglas Mercer. 185-190 [doi]
- GSM DAC with new segmented mismatch shaping techniqueAyman Shabra, Jeffrey Gealow, Paul F. Ferguson Jr.. 191-193 [doi]
- Design considerations and DFT to enable testing of digital interfacesMike Tripp, T. M. Mak, Anne Meixner. 197-205 [doi]
- A digital DFT technique for verifying the static performance of A/D convertersWooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani. 207-210 [doi]
- Design-for-digital-testability 30 MHz second-order Σ-Δ modulatorHao-Chiao Hong. 211-214 [doi]
- RFCMOS technology from 0.25μm to 65nm: the state of the artJohn Pekarik, David R. Greenberg, Basanth Jagannathan, Robert A. Groves, J. R. Jones, Raminderpal Singh, Anil Chinthakindi, Xudong Wang, Matthew J. Breitwisch, Douglas D. Coolbaugh, Peter E. Cottrell, John E. Florkey, Gregory Freeman, R. Krishnasamy. 217-224 [doi]
- Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technologySatoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi. 225-228 [doi]
- Opportunities and challenges in asymmetric device implementation [CMOS device scaling]J. F. Buller, R. van Bentum, J. Cheek, E. Ehrichs, M. Horstmann, S. Searles. 229-232 [doi]
- MOSFET scaling trends and challenges through the end of the roadmapPeter M. Zeitzoff. 233-240 [doi]
- A 3D mixed-mode ESD protection circuit simulation-design methodologyHaolu Xie, Rouying Zhan, Haigang Feng, Guang Chen, Albert Z. Wang, R. Gafiteanu. 243-246 [doi]
- Power network analysis for ESD robustness in a 90nm ASIC design systemCiaran J. Brennan, Joseph N. Kozhaya, Robert A. Proctor. 247-250 [doi]
- Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologiesMarkus P. J. Mergens, John Armer, Phillip Jozwiak, Bart Keppens, Frederic De Ranter, Koen G. Verhaege, R. Kumar. 251-254 [doi]
- Vibrating RF MEMS for next generation wireless applicationsClark T.-C. Nguyen. 257-264 [doi]
- A CMOS VCO with 48% tuning range for modern broadband systemsKostas Manetakis, Darryl Jessie, Chiewcharn Narathong. 265-268 [doi]
- 5-GHz in-phase coupled oscillators with 39% tuning rangeLuca Romanò, V. Minerva, S. Cavalieri d'Oro, Carlo Samori, M. Politi. 269-272 [doi]
- A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitterToru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori. 273-276 [doi]
- On the selection of on-chip inductors for the optimal VCO designYong Zhan, Ramesh Harjani, Sachin S. Sapatnekar. 277-280 [doi]
- A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channelKouichi Nagano, Koji Okamoto, Akira Yamamoto, Hiroki Mouri, Akira Kawabe, Hirokuni Fujiyama, Takashi Morie, Hiroyuki Nakahira, Masahiro Kuramochi, Minoru Ochiai, Kazutoshi Aida, Youichi Ogura, Toshihiko Takahashi, Toru Kakiage, Masao Takiguchi, Takashi Yamamoto, Hiroshi Kamiyama, Yutaka Katabe. 283-286 [doi]
- An improved architecture of the mixed mode clock/data recovery for DVD read channelJungeun Lee, Hyunsu Chae, Hanseung Lee, Maxim Konakov, Junghyun Lee, Jeongwon Lee. 287-290 [doi]
- A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architectureSoo-Hyoung Lee, Jae Young Shin, Ho-Young Lee, Ho-Jin Park, Kristian L. Lund, Karsten Nielsen, Jae-Whui Kim. 291-294 [doi]
- A word-parallel digital associative engine with wide search range based on Manhattan distanceYusuke Oike, Makoto Ikeda, Kunihiro Asada. 295-298 [doi]
- Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications]Sang Gu Kang, Doo Hyung Woo, Hee Chul Lee. 299-302 [doi]
- A 256-element CMOS imaging receiver for free-space optical communicationBrian S. Leibowitz, Bernhard E. Boser, Kristofer S. J. Pister. 303-306 [doi]
- Proactive design for manufacturing (DFM) for nanometer SoC designsCarlo Guardiani, Nicola Dragone, Patrick McNamara. 309-316 [doi]
- Design and development of 130-nanometer ICs for a multi-Gigabit switching network systemAurangzeb Khan, K. Ruparel, C. Joly, V. Ghanta, D. Le, T. Nguyen, J. Yu, Steven Yang, Irfan Ahmed, N. Burnside, V. Chagarlamudi, M. Cheung, F. Chiu, Y. Fan, D. Ge, Jaspal Gill, Pokai Huang, V. Jayapal, Oanh Kim, M. Li, Helder Mak, P. McKeever, S. Nguyen, K. Rajan, S. Riley, Peter Tran, H. Truong, A. Tsou, D. Wang, C. Yang, J. Zhang, X. Zhong. 317-320 [doi]
- An electrically robust method for placing power gating switches in voltage islandsJoseph N. Kozhaya, Luay Bakir. 321-324 [doi]
- Differential transmission line interconnect for high speed and low power global wiringShinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, Kazuya Masu. 325-328 [doi]
- A soft-error hardened latch scheme for SoC in a 90 nm technology and beyondYoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi. 329-332 [doi]
- Analog IP migration using design knowledge extractionSherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy. 333-336 [doi]
- Reviews and future prospects of low-voltage embedded RAMsKiyoo Itoh, Kenichi Osada, Takayda Kawahara. 339-344 [doi]
- BIST controlled variable sense amp timing for 90nm embedded SRAMCiaran J. Brennan, Steven Eustis, John Goss, A. Humphrey, Michael Ouellette, Jeremy Rowland, Michael Fragano. 345-348 [doi]
- Design and implementation of an embedded 512KB level 2 cache subsystemJinuk Luke Shin, Bruce Petrick, Howard Levy, Jinseung Son, Mandeep Singh, Vikas Mathur, Jung-Cheng Yeh, Heesung Choi, Vishal Gupta, Tom Ziaja, Ana Sonia Leon. 349-352 [doi]
- Process variation in nano-scale memories: failure analysis and process tolerant architectureAmit Agarwal, Bipul C. Paul, Kaushik Roy. 353-356 [doi]
- Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modesKenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara. 357-360 [doi]
- Analysis and measurements of EM and substrate coupling effects in common RF integrated circuitsRony E. Amaya, P. H. R. Popplewell, Mark Cloutier, Calvin Plett. 363-366 [doi]
- Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substratesScott Hazenboom, Terri S. Fiez, Kartikeya Mayaram. 367-370 [doi]
- Crosstalk coupling effects of CMOS co-planar spiral inductorsJan Hvolgaard Mikkelsen, Ole K. Jensen, Torben Larsen. 371-374 [doi]
- Noise in passive FET mixers: a simple physical modelSaeed Chehrazi, Rahim Bagheri, Asad A. Abidi. 375-378 [doi]
- Analytical modeling of MOSFET noise parameters for analog and RF applicationsSaman Asgaran, M. Jamal Deen, Chih Hung Chen. 379-382 [doi]
- Enhanced analytic noise model for RF CMOS designJim Koeppe, Ramesh Harjani. 383-386 [doi]
- Measurement and modeling of noise parameters for desensitized low noise amplifiersGaurab Banerjee, David T. Becher, Celia Hung, David J. Allstot, Krishnamurthy Soumyanath. 387-390 [doi]
- Design techniques for a 1-V operation Bluetooth RF transceiverMamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara. 393-400 [doi]
- An ultra-low power 900 MHz RF transceiver for wireless sensor networksAlyosha Molnar, Benson Lu, Steven Lanzisera, Ben W. Cook, Kristofer S. J. Pister. 401-404 [doi]
- A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applicationsNikos Haralabidis, Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, A. Yamanaka, S. Kavadias, G. Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, P. Merakos, I. Bouras, Stamatis Bouras, Sofoklis Plevridis. 405-408 [doi]
- A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANsPengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Chris Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gower, Siegfi Hart, Lam Huynh, Thai Nguyen, Behzad Razavi. 409-412 [doi]
- A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]Mike Hensley, Carroll Speir, Russell Stop, Kevin Behel, Carl Moreland, Greg Patterson, Dan Kelly, Manish Manglani, Michael Elliott, Scott Puckett, Joe Young, Frank Murden. 413-416 [doi]
- Platform IC with embedded via programmable logic for fast customizationLorenzo Cali, Francesco Lertora, Christian Gazzina, Monica Besana, Michele Borgatti. 419-422 [doi]
- Designing a via-configurable regular fabricYajun Ran, Malgorzata Marek-Sadowska. 423-426 [doi]
- Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delayJim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, Troy Dye, Bob Kirk. 427-429 [doi]
- A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interfaceJeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Phlip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan. 431-434 [doi]
- Sequential synthesizable embedded programmable logic cores for system-on-chipAndy Yan, Steven J. E. Wilton. 435-438 [doi]
- A high performance CMOS programmable logic coreYi Han, Larry McMurchie, Carl Sechen. 439-442 [doi]
- MAX II: A low-cost, high-performance LUT-based CPLDPaul Leventis, Brad Vest, Mike Hutton, David M. Lewis. 443-446 [doi]
- Trends and challenges of large scale embedded memoriesTohru Furuyama. 449-456 [doi]
- SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memoriesTomoyuki Ishii, Taro Osabe, Toshiyuki Mine, Toshiaki Sano, Bryan Atwood, Norifumi Kameshiro, Takao Watanabe, Kazuo Yano. 457-463 [doi]
- Advanced ternary CAM circuits on 0.13 μm logic process technologyAlan Roth, Dick Foss, Robert McKenzie, Douglas Perry. 465-468 [doi]
- Pure CMOS one-time programmable memory using gate-ox anti-fuseHiroshi Ito, Toshimasa Namekawa. 469-472 [doi]
- Relative inductance extraction methodKaveh Shakeri, James D. Meindl. 481-484 [doi]
- Efficient capacitance extraction method for interconnects with dummy fillsAtsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda. 485-488 [doi]
- Performance limitation of on-chip global interconnects for high-speed signalingAkira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera. 489-492 [doi]
- EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currentsRong Jiang, Charlie Chung-Ping Chen. 493-496 [doi]
- A surface potential model for predicting substrate noise coupling in integrated circuitsSimon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Kjell O. Jeppson. 497-500 [doi]
- Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 501-504 [doi]
- Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]Masud H. Chowdhury, Yehea I. Ismail. 505-508 [doi]
- Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurementShen Lin, Makoto Nagata, Kenji Shimazake, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang. 509-512 [doi]
- A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swingsKi Young Nam, Sang Min Lee, David K. Su, Bruce A. Wooley. 515-518 [doi]
- A low-voltage low-power sigma-delta modulator with improved performance in overload conditionHugh Thompson, Mike Hufford, William Evans, Eric Naviasky. 519-522 [doi]
- Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCsXuesheng Wang, Yuhua Guo, Un-Ku Moon, Gabor C. Temes. 523-526 [doi]
- Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulatorsSusana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos. 527-530 [doi]
- Efficient sampling of reference noise in a switched capacitor ΣΔ ADCIvan John O'Connell, Colin Lyden. 531-534 [doi]
- A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital processJinseok Koh, Khurram Muhammad, Robert B. Staszewski, Gabriel Gomez, Baher Horoun. 535-538 [doi]
- Design and manufacturability aspect of SOI CMOS RFICsJonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer. 541-548 [doi]
- An all-digital universal RF transmitter [CMOS RF modulator and PA]Poojan Wagh, Pallab Midya, Pat Rakers, James Caldwell, Tony Schooler. 549-552 [doi]
- A 5-GHz silicon bipolar transmitter front-end for wireless LAN applicationsAlessandro Italia, Luca La Paglia, Antonino Scuderi, Francesco Carrara, Egidio Ragonese, G. Palmisano. 553-556 [doi]
- A CMOS high efficiency +22 dBm linear power amplifierYongwang Ding, Ramesh Harjani. 557-560 [doi]
- A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 μm CMOSAbbas Komijani, Ali Hajimiri. 561-564 [doi]
- A highly integrated quad band low EVM polar modulation transmitter for GSM/EDGE applicationsAristotele Hadjichristos, Joel Walukas, Nikolaus Klemmer, Wen Suter, Scott Justice, Satish Uppathil, Gary Scott. 565-568 [doi]
- High performance open-loop AM modulator designed for power control of E-GPRS polar modulated power amplifierDavid R. Pehlke, Aristotele Hadjichristos, Scott Justice. 569-572 [doi]
- Sandblaster low power DSP [parallel DSP arithmetic microarchitecture]John Glossner, Kai Chirca, Michael J. Schulte, Haoran Wang, Nasir Nasimzada, David Har, Shenghong Wang, A. Joseph Hoane, Gary Nacer, Mayan Moudgill, Stamatis Vassiliadis. 575-581 [doi]
- A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processorsYoung-Don Bae, In-Cheol Park. 583-586 [doi]
- A baseband processor for pulsed ultra-wideband signalsRaúl Blázquez, Puneet P. Newaskar, Fred S. Lee, Anantha P. Chandrakasan. 587-590 [doi]
- The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receiversMehmet R. Yuce, Wentai Liu, Bhaskar Bharath, John Damiano, Paul D. Franzon. 591-594 [doi]
- A XiRisc-based SoC for embedded DSP applicationsMassimo Bocchi, Claudia De Bartolomeis, Claudio Mucci, Fabio Campi, Andrea Lodi 0002, Mario Toma, Roberto Canegallo, Roberto Guerrieri. 595-598 [doi]
- An image recognition processor using dynamically reconfigurable ALUNaoto Miyamoto, Koji Kotani, Kazuyuki Maruo, Tadahiro Ohmi. 599-602 [doi]
- A broadband low-noise front-end amplifier for ultra wideband in 0.13 μm CMOSRanjit Gharpurey. 605-608 [doi]
- A DC-10GHz linear-in-dB attenuator in 0.13 μm CMOS technologyHakan Dogan, Robert G. Meyer, Ali M. Niknejad. 609-612 [doi]
- A Ku-band monolithic tuner-LNB for satellite applications [low noise block down-converter]Giovanni Girlando, Tino Copani, Santo A. Smerzi, Giuseppe Palmisano. 613-616 [doi]
- A 21-27GHz self-shielded 4-way power-combining PA balunTak Shun D. Cheung, John R. Long, Youri Tretiakov, David L. Harame. 617-620 [doi]
- Improved method for measuring frequency ratios in GSM mobile phonesPeter Bode, Alexander Lampe, Markus Helfenstein, Michael Gollnick. 621-624 [doi]
- rd order 3-bit-FIR noise shapers in 90nm CMOSAshoke Ravi, Ralph E. Bishop, L. Richard Carley, Krishnamurthy Soumyanath. 625-628 [doi]
- A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiverSander L. J. Gierkink, Dandan Li, Robert C. Frye, Vito Boccuzzi. 629-632 [doi]
- Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage referencePhilip K. T. Mok, Ka Nang Leung. 635-642 [doi]
- Optimum area allocation for minimum mismatch [IC device area optimization]B. Robert Gregoire. 643-646 [doi]
- A programmable floating-gate voltage reference in 0.5 μm CMOSSeth A. Cook, Kent D. Layton, William J. Marble, Donald T. Comer, David J. Comer, Craig Petrie. 647-650 [doi]
- A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearityRavi Chawla, Abhishek Bandyopadhyay, Venkatesh Srinivasan, Paul E. Hasler. 651-654 [doi]
- An 8bit 3GHz Si/SiGe HBT sample-and-holdJonathan C. Jensen, Lawrence E. Larson. 655-658 [doi]
- Variable gain differential current feedback amplifierIvan Koudar. 659-662 [doi]
- The crazy mixed up world of silicon debug [IC validation]Doug Josephson, Bob Gottlieb. 665-670 [doi]
- Infrastructure for modular SOC testingErik Jan Marinissen, Tom Waayers. 671-678 [doi]
- System in package "the rebirth of SIP"Kenneth M. Brown. 681-686 [doi]
- Factors influencing the design of microsystemsLeland Spangler. 687-691 [doi]
- Low-noise CMOS integrated sensing electronics for capacitive MEMS strain sensorsMichael A. Suster, Jun Guo, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young. 693-696 [doi]
- 10× improvement of power transmission over free space using integrated antennas on silicon substratesJau-Jr Lin, Xiaoling Guo, Ran Li, Jason Branch, Joe E. Brewer, Kenneth K. O. 697-700 [doi]
- A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductorDimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Lars Aspemyr, Andries J. Scholten, Piet Wambacq, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt. 701-704 [doi]
- A CMOS 3D camera with millimetric depth resolutionCristiano Niclass, Alexis Rochas, Pierre-André Besse, Edoardo Charbon. 705-708 [doi]
- Power estimation and thermal budgeting methodology for FPGAsHenry Y. Lui, Chong H. Lee, Rakesh H. Patel. 711-714 [doi]
- Low leakage circuit design for FPGAsLuca Ciccarelli, Andrea Lodi 0002, Roberto Canegallo. 715-718 [doi]
- A novel low-power FPGA routing switchJason Helge Anderson, Farid N. Najm. 719-722 [doi]