Peter Bendix - researchr alias

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Viewing Publication 1 - 13 from 13

2005

ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invitedYoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman. iwsoc 2005: 47-53 [doi]

2004

Practical aspects of MOS transistor model "accuracy" in modern CMOS technologyPeter Bendix, Daniel Foty, David Pachura. icecsys 2004: 642-645 [doi]

RF distortion analysis with compact MOSFET modelsPeter Bendix, Pat Rakers, P. Wagh, Laurent Lemaitre, W. Grabinski, Colin C. McAndrew, X. Gu, Gennady Gildenblat. cicc 2004: 9-12 [doi]

Advanced compact models: gateway to modern CMOS designGennady Gildenblat, Colin C. McAndrew, Hailing Wang, Weimin Wu, Daniel Foty, Laurent Lemaitre, Peter Bendix. icecsys 2004: 638-641 [doi]

Design of ESD power protection with diode structures for mixed-power supply systemsJaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang. jssc, 39(1):260-264, 2004. [doi]

Prediction of interconnect adjacency distribution: derivation, validation, and applicationsPayman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix. slip 2004: 99-106 [doi]

2003

A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC LinesYannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix. iccad 2003: 665-671 [doi]

Chip-level charged-device modeling and simulation in CMOS integrated circuitsJaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang. tcad, 22(1):67-81, 2003. [doi]

2001

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