Abstract is missing.
- Adapative Error Protection for Energy EfficiencyLin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 2-7 [doi]
- SAMBA-Bus: A High Performance Bus Architecture for System-on-ChipsRuibing Lu, Cheng-Kok Koh. 8-12 [doi]
- The Y-Architecture for On-Chip Interconnect: Analysis and MethodologyHongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao. 13-20 [doi]
- Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time SystemsVishnu Swaminathan, Krishnendu Chakrabarty. 21-25 [doi]
- Approaching the Maximum Energy Saving on Embedded Systems with Multiple VoltagesShaoxiong Hua, Gang Qu. 26-29 [doi]
- Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded SystemsLe Yan, Jiong Luo, Niraj K. Jha. 30-38 [doi]
- RTL Power Optimization with Gate-Level AccuracyQi Wang, Sumit Roy. 39-45 [doi]
- Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive ApplicationsChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 46-53 [doi]
- Achieving Design Closure Through Delay Relaxation ParameterAnkur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh. 54-57 [doi]
- Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware ThreadingBrian Swahn, Soha Hassoun. 58-65 [doi]
- Bus-Driven FloorplanningHua Xiang, Xiaoping Tang, Martin D. F. Wong. 66-73 [doi]
- A Novel Geometric Algorithm for Fast Wire-Optimized FloorplanningPeter G. Sassone, Sung Kyu Lim. 74-80 [doi]
- Placement Method Targeting Predictability Robustness and PerformanceCristinel Ababei, Kia Bazargan. 81-85 [doi]
- Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed ApproachBrent Goplen, Sachin S. Sapatnekar. 86-90 [doi]
- Partial Core Encryption for Performance-Efficient Test of SOCsOzgur Sinanoglu, Alex Orailoglu. 91-94 [doi]
- TAM Optimization for Mixed-Signal SOCs using Analog Test WrappersAnuja Sehgal, Sule Ozev, Krishnendu Chakrabarty. 95-99 [doi]
- Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power ConstraintsYu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske. 100-106 [doi]
- Moment-Based Power Estimation in Very Deep Submicron TechnologiesAlberto GarcĂa Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner. 107-112 [doi]
- IDAP: A Tool for High Level Power Estimation of Custom Array StructuresMahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir. 113-119 [doi]
- Design and CAD Challenges in sub-90nm CMOS TechnologiesKerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri. 129-137 [doi]
- Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline EvaluationIn-Cheol Park, Se-Hyeon Kang, Yongseok Yi. 138-141 [doi]
- A Framework for Constrained Functional VerificationJun Yuan, Carl Pixley, Adnan Aziz, Ken Albin. 142-145 [doi]
- Generator-based VerificationYunshan Zhu, James H. Kukula. 146-153 [doi]
- Efficient Generation of Monitor Circuits for GSTE Assertion GraphsAlan J. Hu, Jeremy Casas, Jin Yang. 154-160 [doi]
- Weibull Based Analytical Waveform ModelChirayu S. Amin, Florentin Dartu, Yehea I. Ismail. 161-168 [doi]
- Equivalent Waveform Propagation for Static Timing AnalysisMasanori Hashimoto, Yuji Yamada, Hidetoshi Onodera. 169-175 [doi]
- Timing Analysis in Presence of Power Supply and Ground Voltage VariationsRubil Ahmadi, Farid N. Najm. 176-183 [doi]
- Vectorless Analysis of Supply Noise Induced Delay VariationSanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. 184-192 [doi]
- Array Composition and Decomposition for Optimizing Embedded ApplicationsGuilin Chen, Mahmut T. Kandemir, A. Nadgir, Ugur Sezer. 193-196 [doi]
- Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software DesignJunhyung Um, Taewhan Kim. 197-200 [doi]
- Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional PartitioningJinfeng Liu, Pai H. Chou. 201-208 [doi]
- Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded SystemsYing Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan. 209-214 [doi]
- Retiming for Wire Pipelining in System-On-ChipChuan Lin, Hai Zhou. 215-220 [doi]
- Retiming with Interconnect and Gate DelayChris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu. 221-226 [doi]
- Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication ChannelsRuibing Lu, Cheng-Kok Koh. 227-231 [doi]
- Clock Scheduling and Clocktree Construction for High Performance ASICSStephan Held, Bernhard Korte, Jens MaĂźberg, Matthias Ringe, Jens Vygen. 232-240 [doi]
- Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit SpecificationGuido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich. 241-246 [doi]
- A Generalized Method for Computing Oscillator Phase Noise SpectraPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 247-250 [doi]
- Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit SimulationFabrice Veersé. 251-255 [doi]
- Fredkin/Toffoli Templates for Reversible Logic SynthesisDmitri Maslov, Gerhard W. Dueck, D. Michael Miller. 256-261 [doi]
- Evaluation of Placement Techniques for DNA Probe Array LayoutAndrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky. 262-269 [doi]
- Physical And Reduced-Order Dynamic Analysis of MEMSS. K. De, Narayan R. Aluru. 270-274 [doi]
- Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP DesignsClaire Fang Fang, Rob A. Rutenbar, Tsuhan Chen. 275-282 [doi]
- A Scalable Application-Specific Processor Synthesis MethodologyFei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 283-290 [doi]
- INSIDE: INstruction Selection/Identification & Design Exploration for Extensible ProcessorsNewton Cheung, Sri Parameswaran, Jörg Henkel. 291-298 [doi]
- An Enhanced Multilevel Algorithm for Circuit PlacementTony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze. 299-306 [doi]
- Fractional Cut: Improved Recursive Bisection PlacementAmeya R. Agnihotri, Mehmet Can Yildiz, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden. 307-310 [doi]
- On Whitespace and Stability in Mixed-Size Placement and Physical SynthesisSaurabh N. Adya, Igor L. Markov, Paul Villarrubia. 311-319 [doi]
- SATORI - A Fast Sequential SAT Engine for CircuitsMadhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng. 320-325 [doi]
- CAMA: A Multi-Valued Satisfiability SolverCong Liu, Andreas Kuehlmann, Matthew W. Moskewicz. 326-333 [doi]
- The Compositional Far Side of Image ComputationChao Wang, Gary D. Hachtel, Fabio Somenzi. 334-341 [doi]
- Cache Optimization For Embedded Processor Cores: An Analytical ApproachArijit Ghosh, Tony Givargis. 342-347 [doi]
- Fault-Tolerant Techniques for Ambient Intelligent Distributed SystemsDiana Marculescu, Nicholas H. Zamora, Phillip Stanley-Marbell, Radu Marculescu. 348-355 [doi]
- Performance Efficiency of Context-Flow System-on-Chip PlatformRami Beidas, Jianwen Zhu. 356-362 [doi]
- Amplification of Ultrawideband SignalsWon Namgoong, Jongrit Lerdworatawee. 363-366 [doi]
- A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCsMohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei. 367-370 [doi]
- Systematic Design for Power Minimization of Pipelined Analog-to-Digital ConvertersReza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei. 371-374 [doi]
- A Framework for Designing Reusable Analog CircuitsDean Liu, Stefanos Sidiropoulos, Mark Horowitz. 375-381 [doi]
- A Fast Crosstalk- and Performance-Driven Multilevel Routing SystemTsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee. 382-387 [doi]
- A Min-Cost Flow Based Detailed Router for FPGAsSeokjin Lee, Yongseok Cheon, Martin D. F. Wong. 388-393 [doi]
- Length-Matching Routing for High-Speed Printed Circuit BoardsMuhammet Mustafa Ozdal, Martin D. F. Wong. 394-400 [doi]
- Analytical Bound for Unwanted Clock Skew due to Wire Width VariationAnand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu. 401-407 [doi]
- Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction RefinementChao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi. 408-415 [doi]
- Iterative Abstraction using SAT-based BMC with Proof AnalysisAarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar. 416-423 [doi]
- Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous CircuitsCurtis A. Nelson, Chris J. Myers, Tomohiro Yoneda. 424-432 [doi]
- System Level Design and Verification Using a Synchronous LanguageGĂ©rard Berry, Michael Kishinevsky, Satnam Singh. 433-440 [doi]
- Noise Analysis for Optical Fiber Communication SystemsAlper Demir. 441-445 [doi]
- Analog Macromodeling using Kernel MethodsJoel R. Phillips, JoĂŁo Afonso, Arlindo L. Oliveira, Luis Miguel Silveira. 446-453 [doi]
- A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog CircuitsPeng Li, Xin Li, Yang Xu, Lawrence T. Pileggi. 454-462 [doi]
- Incremental Placement for Timing OptimizationWonjoon Choi, Kia Bazargan. 463-466 [doi]
- A Trade-off Oriented Placement ToolHuaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh. 467-471 [doi]
- Optimality and Stability Study of Timing-Driven Placement AlgorithmsJason Cong, Michail Romesis, Min Xie. 472-479 [doi]
- A Probabilistic-Based Design Methodology for Nanoscale ComputationR. Iris Bahar, Joseph L. Mundy, Jie Chen. 480-486 [doi]
- Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit SimulationArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy. 487-490 [doi]
- Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V CharacteristicsJiayong Le, Lawrence T. Pileggi, Anirudh Devgan. 491-496 [doi]
- A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated CircuitsSantanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu. 497-503 [doi]
- A Game Theoretic Approach to Dynamic Energy Minimization in Wireless TransceiversAli Iranli, Hanif Fatemi, Massoud Pedram. 504-509 [doi]
- Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy MinimizationGirish Varatkar, Radu Marculescu. 510-517 [doi]
- LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction CachesPraveen Kalla, Xiaobo Sharon Hu, Jörg Henkel. 518-522 [doi]
- Compiler-Based Register Name Adjustment for Low-Power Embedded ProcessorsPeter Petrov, Alex Orailoglu. 523-528 [doi]
- Gradual Relaxation Techniques with Applications to Behavioral SynthesisZhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong. 529-535 [doi]
- Architectural Synthesis Integrated with Global Placement for Multi-Cycle CommunicationJason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang. 536-543 [doi]
- Binding, Allocation and Floorplanning in Low Power High-Level SynthesisAnsgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel. 544-550 [doi]
- A High-level Interconnect Power Model for Design Space ExplorationPallav Gupta, Lin Zhong, Niraj K. Jha. 551-559 [doi]
- A Probabilistic Approach to Buffer InsertionVishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava. 560-567 [doi]
- Simultaneous Analytic Area and Power Optimization for Repeater InsertionGiuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten. 568-573 [doi]
- Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop InsertionWeiping Liao, Lei He. 574-580 [doi]
- Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire SizingRuiming Li, Dian Zhou, Jin Liu, Xuan Zeng. 581-587 [doi]
- Dynamic Data-bit Memory Built-In Self- RepairMichael Nicolaidis, Nadir Achouri, Slimane Boutobza. 588-594 [doi]
- FAME: A Fault-Pattern Based Memory Failure Analysis FrameworkKuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu. 595-598 [doi]
- Hardware/Software Co-testing of Embedded Memories in Complex SOCsBai Hong Fang, Qiang Xu, Nicola Nicolici. 599-606 [doi]
- Block-based Static Timing Analysis with UncertaintyAnirudh Devgan, Chandramouli V. Kashyap. 607-614 [doi]
- AU: Timing Analysis Under UncertaintySarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw. 615-620 [doi]
- Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like TraversalHongliang Chang, Sachin S. Sapatnekar. 621-626 [doi]
- Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level CachesNam Sung Kim, David Blaauw, Trevor N. Mudge. 627-632 [doi]
- Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone SystemsPhillip Stanley-Marbell, Diana Marculescu. 633-640 [doi]
- Dynamic Platform Management for Configurable Platform-Based System-on-ChipsKrishna Sekar, Kanishka Lahiri, Sujit Dey. 641-649 [doi]
- A General S-Domain Hierarchical Network Reduction AlgorithmSheldon X.-D. Tan. 650-657 [doi]
- Branch Merge Reduction of RLCM NetworksBernard N. Sheehan. 658-664 [doi]
- A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC LinesYannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix. 665-671 [doi]
- Mixed Signal DFT: A Concise OverviewBozena Kaminska, Karim Arabi. 672-680 [doi]
- Manufacturing-Aware Physical DesignPuneet Gupta, Andrew B. Kahng. 681-688 [doi]
- A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational CircuitsRahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown. 689-692 [doi]
- Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module LevelYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee. 693-700 [doi]
- On the Interaction Between Power-Aware FPGA CAD AlgorithmsJulien Lamoureux, Steven J. E. Wilton. 701-708 [doi]
- A Theory of Non-Deterministic NetworksAlan Mishchenko, Robert K. Brayton. 709-717 [doi]
- Stable Multiway Circuit Partitioning for ECOYongseok Cheon, Seokjin Lee, Martin D. F. Wong. 718-725 [doi]
- Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree MinimizationNavaratnasothie Selvakkumaran, George Karypis. 726-733 [doi]
- An Algorithmic Approach for Generic Parallel AddersJianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng. 734-740 [doi]
- FROSTY: A Fast Hierarchy Extractor for Industrial CMOS CircuitsLei Yang, C.-J. Richard Shi. 741-747 [doi]
- Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet AnalysisAbhishek Singh, Jitin Tharian, Jim Plusquellic. 748-753 [doi]
- Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault CoveragePuneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma. 754-759 [doi]
- Static Verification of Test Vectors for IR Drop FailureAman Kokrady, C. P. Ravikumar. 760-764 [doi]
- ATPG for Noise-Induced Switch Failures in Domino LogicRahul Kundu, R. D. (Shawn) Blanton. 765-769 [doi]
- Statistical Verification of Power Grids Considering Process-Induced Leakage Current VariationsImad A. Ferzli, Farid N. Najm. 770-777 [doi]
- A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching ActivityAlessandra Nardi, Haibo Zeng, Joshua L. Garrett, Luca Daniel, Alberto L. Sangiovanni-Vincentelli. 778-785 [doi]
- SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel EvaluationTsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen. 786-792 [doi]
- SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling EffectsZhao Li, C.-J. Richard Shi. 793-800 [doi]
- Multi-Domain Clock Skew SchedulingKaushik Ravindran, Andreas Kuehlmann, Ellen Sentovich. 801-808 [doi]
- Clock Period Minimization of Non-Zero Clock Skew CircuitsShih-Hsu Huang, Yow-Tyng Nieh. 809-812 [doi]
- Minimum-Area Sequential Budgeting for FPGAChao-Yang Yeh, Malgorzata Marek-Sadowska. 813-817 [doi]
- ILP Models for the Synthesis of Asynchronous Control CircuitsJosep Carmona, Jordi Cortadella. 818-826 [doi]
- Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral RulesTraianos Yioultsis, Anne Woo, Andreas C. Cangellaris. 827-834 [doi]
- Analytic Modeling of Interconnects for Deep Sub-Micron CircuitsDinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen. 835-842 [doi]
- A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D StructuresBen Song, Zhenhai Zhu, John D. Rockway, Jacob White. 843-847 [doi]
- Switch-Factor Based Loop RLC Modeling for Efficient Timing AnalysisYu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester. 848-854 [doi]
- On Compacting Test Response Data Containing Unknown ValuesChen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer. 855-862 [doi]
- Adjustable Width Linear Combinational Scan Vector DecompressionC. V. Krishna, Nur A. Touba. 863-866 [doi]
- On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability LogicIrith Pomeranz, Sudhakar M. Reddy. 867-873 [doi]
- Formal Methods for Dynamic Power ManagementRajesh K. Gupta, Sandy Irani, Sandeep K. Shukla. 874-882 [doi]
- Large-Scale Circuit Placement: Gap and PromiseJason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan. 883-890 [doi]
- Multi-Million Gate FPGA Physical Design ChallengesMaogang Wang, Abhishek Ranjan, Salil Raje. 891-899 [doi]
- Statistical Timing Analysis for Intra-Die Process Variations with Spatial CorrelationsAseem Agarwal, David Blaauw, Vladimir Zolotov. 900-907 [doi]
- A Statistical Gate-Delay Model Considering Intra-Gate VariabilityKen-ichi Okada, Kento Yamaoka, Hidetoshi Onodera. 908-913 [doi]
- Statistical Clock Skew Analysis Considering Intra-Die Process VariationsAseem Agarwal, David Blaauw, Vladimir Zolotov. 914-921 [doi]
- SOI Transistor Model for Fast Transient SimulationD. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel. 120128 [doi]