Jeffrey L. Burns - researchr alias

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Viewing Publication 1 - 21 from 21

2017

Panel discussions: "Cool chips for the next decade"Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash. coolchips 2017: 1-3 [doi]

2011

Technology trends and implications on SoC designJeffrey L. Burns. socc 2011: 386 [doi]

2004

Resonant clocking using distributed parasitic capacitanceAlan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown. jssc, 39(9):1520-1528, 2004. [doi]

Analysis and Optimization of Enhanced MTCMOS SchemeRahul M. Rao, Jeffrey L. Burns, Richard B. Brown. vlsid 2004: 234-239 [doi]

2003

Leakage and leakage sensitivity computation for combinational circuitsEmrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns. islped 2003: 96-99 [doi]

A semi-custom voltage-island technique and its application to high-speed serial linksJuan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman. islped 2003: 60-65 [doi]

Dynamically Optimized Synchronous Communication for Low Power System on Chip DesignsVikas Chandra, Gary D. Carpenter, Jeffrey L. Burns. iccd 2003: 134-139 [doi]

Efficient techniques for gate leakage estimationRahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown. islped 2003: 100-103 [doi]

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologiesRahul M. Rao, Jeffrey L. Burns, Richard B. Brown. esscirc 2003: 313-316 [doi]

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational CircuitsRahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown. iccad 2003: 689-692 [doi]

2002

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scalingKevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns. jssc, 37(11):1441-1447, 2002. [doi]

1999

Performance Driven Synthesis for Pass-Transistor LogicTai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns. vlsid 1999: 372-377

1998

C5M-a control-logic layout synthesis system for high-performance microprocessorsJeffrey L. Burns, Jack A. Feldman. tcad, 17(1):14-23, 1998. [doi]

Area-oriented synthesis for pass-transistor logicRajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns. In ICCD. 1998: 160-167 [doi]

Designing for a gigahertz [guTS integer processor]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi. micro, 18(3):66-74, 1998. [doi]

Design methodology for a 1.0 GHz microprocessorStephen D. Posluszny, N. Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, K. Lee, D. Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo. In ICCD. 1998: 17-23 [doi]

1997

C5M - a control logic layout synthesis system for high-performance microprocessorsJeffrey L. Burns, Jack A. Feldman. ispd 1997: 110-115 [doi]

1994

The Effect of Wire Length Minimization on YieldVenkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns. dft 1994: 97-105

1988

Techniques for multilayer channel routingDouglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma. tcad, 7(6):698-712, 1988. [doi]

1986

Chameleon: a new multi-layer channel routerDouglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli. dac 1986: 495-502 [doi]

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Publications by 'Jeffrey L. Burns'

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2017

2011

2004

2003

2002

1999

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1997

1994

1988

1986

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