Abstract is missing.
- Fundamentals of parallel logic simulationRobert J. Smith II. 2-12 [doi]
- Statistics on logic simulationKenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing. 13-19 [doi]
- Exploiting parallelism in a switch-level simulation machineEdward H. Frank. 20-26 [doi]
- A version server for computer-aided design dataRandy H. Katz, M. Anwarrudin, Ellis E. Chang. 27-33 [doi]
- Semantics of CAD objects for generalized databasesDominique Rieu, Gia Toan Nguyen. 34-40 [doi]
- DOSS: a storage system for design dataShlomo Weiss, Katie Rotzell, Tom Rhyne, Arny Goldfein. 41-47 [doi]
- A design utility manager: the ADAM planning engineDavid Knapp, Alice C. Parker. 48-54 [doi]
- VLSI CAD tool integration using the Ulysses environmentMichael L. Bushnell, Stephen W. Director. 55-61 [doi]
- An expert-system paradigm for designForrest Brewer, Daniel Gajski. 62-68 [doi]
- Tutorial on parallel processing for design automation applications (tutorial session)J. M. Hancock, S. DasGupta. 69-77 [doi]
- Logic synthesis and optimization benchmarks for the 1986 Design Automation ConferenceAart J. de Geus. 78 [doi]
- SOCRATES: a system for automatically synthesizing and optimizing combinational logicDavid Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel. 79-85 [doi]
- Technology adaption in logic synthesisWilliam H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen. 94-100 [doi]
- A new algorithm for floorplan designD. F. Wong, C. L. Liu. 101-107 [doi]
- A linear algorithm to find a rectangular dual of a planar triangulated graphJayaram Bhasker, Sartaj Sahni. 108-114 [doi]
- Two-dimensional compaction by zone refining Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin. 115-122 [doi]
- Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layoutSching L. Lin, Jonathan Allen. 123-130 [doi]
- An object-oriented visual simulator for microprogram developmentAkira Sugimoto, Shigeru Abe, Masahiro Kuroda, Yukio Kato. 138-144 [doi]
- A monitor for complex CAD systemsAlberto Di Janni. 145-151 [doi]
- Automating the generation of interactive interfacesKatherine Hammer, Dan Radin, Tom Rhyne, John Hardin, Tina Timmerman. 152-158 [doi]
- SLS - a fast switch level simulator for verification and fault coverage analysisZeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman. 164-170 [doi]
- CINNAMON: coupled integration and nodal analysis of MOS networksLuís M. Vidigal, Sani R. Nassif, Stephen W. Director. 179-185 [doi]
- A workstation-mixed model circuit simulatorPeter Odryna, Kevin Nazareth, Carl Christensen. 186-192 [doi]
- Generating essential primes for a Boolean function with multiple-valued inputsY. S. Kuo, W. K. Chou. 193-199 [doi]
- A new method for verifying sequential circuitsKenneth J. Supowit, Steven J. Friedman. 200-207 [doi]
- A logic verifier based on Boolean comparisonGotaro Odawara, Masahiro Tomita, Osamu Okuzawa, Tomomichi Ohta, Zhen-quan Zhuang. 208-214 [doi]
- Reasoning about digital systems using temporal logicS. Bapat, G. Venkatesh. 215-219 [doi]
- SCAT - a new statistical timing verifier in a silicon compiler systemManfred Glesner, Johannes Schuck, R. B. Steck. 220-226 [doi]
- An accuration delay modeling technique for switch-level timing verificationSeung Ho Hwang, Young-Hwan Kim, A. Richard Newton. 227-233 [doi]
- Yield of VLSI circuits: myths vs. reality (panel)Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper. 234-235 [doi]
- Robust test generation algorithm for stuck-open fault in CMOS circuitsWeiwei Mao, Xieting Ling. 236-242 [doi]
- Transistor-level test generation for physical failures in CMOS circuitsHsi-Ching Shih, Jacob A. Abraham. 243-249 [doi]
- A heuristic chip-level test generation algorithmDaniel S. Barclay, James R. Armstrong. 257-262 [doi]
- A new synthesis for the MIMOLA software systemPeter Marwedel. 271-277 [doi]
- Synthesis of VLSI systems with the CAMAD design aidZebo Peng. 278-284 [doi]
- Synthesis of concurrent modular controllers from algorithmic descriptionsR. Brück, Bernd Kleinjohann, Thomas Kathöfer, Franz J. Rammig. 285-292 [doi]
- Simulated annealing and combinatorial optimizationSurendra Nahar, Sartaj Sahni, Eugene Shragowitz. 293-299 [doi]
- On the relative placement and the transportation problem for standard-cell layoutKnut M. Just, Jürgen M. Kleinhans, Frank M. Johannes. 308-313 [doi]
- Analysis of placement procedures for VLSI standard cell layoutMark R. Hartoog. 314-319 [doi]
- A tutorial introduction to the electronic design interchange format (tutorial session)John P. Eurich. 327-333 [doi]
- A unified treatment of PLA faults by Boolean differencesWilfried Daehn. 334-338 [doi]
- Design-for-testability of PLA s using statistical coolingMichiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker. 339-345 [doi]
- Use of the subscripted DALG in submodule testing with applications in cellular arraysM. Ladjadj, J. F. McDonald, D.-H. Ho, W. Murray. 346-353 [doi]
- Principles of design automatioon system for very large scale computer designYasuhiro Ohno, Masayuki Miyoshi, Norio Yamada, Toshihiko Odaka, Tokinori Kozawa, Kooichiro Ishihara. 354-359 [doi]
- An extensive logic simulation method of very large scale computer designMasayuki Miyoshi, Yoshio Ooshima, Atsushi Sugiyama, Nobuhiko Onizuka, Nobutaka Amano. 360-365 [doi]
- Computer aided (CA) tools integration and related standards development (panel session)Roger J. Pachter, R. Smith, Ronald Waxman, J. Hines, H. G. Adhead, L. O Connell, M. Shahdad, John P. Eurich. 372-373 [doi]
- Efficient spare allocation in reconfigurable arraysSy-Yen Kuo, W. Kent Fuchs. 385-390 [doi]
- An effective delay analysis system for a large scale computer designReiji Toyoshima, Yoshimitsu Takiguchi, Kazumi Matsumoto, Hidetomo Hongou, Mashiro Hashimoto, Ryotaro Kamikawai, Katsuhiko Takizawa. 398-403 [doi]
- Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIsYasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba. 404-410 [doi]
- A time and space efficient net extractorSurendra Nahar, Sartaj Sahni. 411-417 [doi]
- Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruningR. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby. 418-424 [doi]
- A technology independent approach to hierarchical IC layout extractionAhsan Bootehsaz, Robert A. Cottrel. 425-431 [doi]
- TimberWolf3.2: a new standard cell placement and global routing packageCarl Sechen, Alberto L. Sangiovanni-Vincentelli. 432-439 [doi]
- Vanguard: a chip physical design systemPeter S. Hauge, Ellen J. Yoffa. 440-446 [doi]
- Automated layout synthesis in the YASC silicon compilerDavid E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin. 447-453 [doi]
- Sehwa: a program for synthesis of pipelinesNohbyung Park, Alice C. Parker. 454-460 [doi]
- MAHA: a program for datapath synthesisAlice C. Parker, Jorge T. Pizarro, Mitch J. Mlinar. 461-466 [doi]
- PLEST: a program for area estimation of VLSI integrated circuitsFadi J. Kurdahi, Alice C. Parker. 467-473 [doi]
- Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptionsMichael C. McFarland. 474-480 [doi]
- Hierarchial global wiring for custom chip designW. K. Luk, Donald T. Tang, C. K. Wong. 481-489 [doi]
- Chameleon: a new multi-layer channel routerDouglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli. 495-502 [doi]
- Flow graph representationAlex Orailoglu, Daniel Gajski. 503-509 [doi]
- A design rule database system to support technology-adaptable applicationsJúlio S. Aude, Hilary J. Kahn. 510-516 [doi]
- STL - a high level language for simulation and testJohn Ivie, Kwok-Woon Larry Lai. 517-523 [doi]
- GENERIC: a silicon compiler support languageJon A. Solworth. 524-530 [doi]
- Knowlege-based expert systems and their application (tutorial sessionWilliam P. Birmingham, Rostam Joobbani, Jin Kim. 531-539 [doi]
- On fault modeling for dynamic MOS circuitsHans-Joachim Wunderlich, Wolfgang Rosenstiel. 540-546 [doi]
- Effectiveness of heuristics measures for automatic test pattern generationSanjay J. Patel, Janak H. Patel. 547-552 [doi]
- Mixed-level fault coverage estimationHi-Keung Tony Ma, Alberto L. Sangiovanni-Vincentelli. 553-559 [doi]
- Optimal order of the VLSI IC testing sequenceWojciech Maly. 560-566 [doi]
- Multiprocessor-based placement by simulated annealingSaul A. Kravitz, Rob A. Rutenbar. 567-573 [doi]
- A new routing algorithm and its hardware implementationTakumi Watanabe, Yoshi Sugiyama. 574-580 [doi]
- HAL II: a mixed level hardware logic simulation systemShigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike. 581-587 [doi]
- An empirical analysis of the performance of a multiprocessor-based circuit simulatorGeorge K. Jacob, A. Richard Newton, Donald O. Pederson. 588-593 [doi]
- A rule-based logic circuit synthesis system for CMOS gate arraysTakao Saito, Hiroyuki Sugimoto, Masami Yamazaki, Nobuaki Kawato. 594-600 [doi]
- Flute - a floorplanning agent for full custom VLSI designHiroyuki Watanabe, Bryan D. Ackland. 601-607 [doi]
- Knowledge-based optimal IIL generator from conventional logic circuit descriptionsT. Watanabe, T. Masuishi, T. Nishiyama, N. Horie. 608-614 [doi]
- PEARL: an expert system for power supply layoutEdward J. DeJesus, James P. Callan, Curtis R. Whitehead. 615-621 [doi]
- Automatic placement a review of current techniques (tutorial session)Bryan Preas, Patrick G. Karger. 622-629 [doi]
- Floor planning systems (panel session)Howard S. Rifkin, William Heller, Steve Law, Misha Burich, Alberto L. Sangiovanni-Vincentelli. 630 [doi]
- GENIE: a generalized array optimizer for VLSI synthesisSrinivas Devadas, A. Richard Newton. 631-637 [doi]
- An implementation of a state assignment heuristicAlan J. Coppola. 643-649 [doi]
- Escher - a geometrical layout system for recursively defined circuitsEdmund M. Clarke, Yulin Feng. 650-653 [doi]
- MADMACS: a new VLSI layout macro editorPatrice Frison, Eric Gautrin. 654-658 [doi]
- A language for describing rectilinear Steiner tree configurationsAntony P.-C. Ng, Clark D. Thompson, Prabhakar Raghavan. 659-662 [doi]
- Dual quadtree representation for VLSI designsS. K. Nandy, L. V. Ramakrishnan. 663-666 [doi]
- Precedent-based manipulation of VLSI structuresRichard H. Lathrop, Robert S. Kirk. 667-670 [doi]
- A frame based system for representing knowledge about VLSI design: a proposalW. Stephen Adolph, Hassan K. Reghbati, Amar Sanmugasunderam. 671-676 [doi]
- A rule-based approach to unifying functional and fault simulation and timing verificationSumit Ghosh. 677-682 [doi]
- Delay reduction using simulated annealingJonathan D. Pincus, Alvin M. Despain. 690-695 [doi]
- A new approach to multi-layer PCB routing with short viasJ. Fernando Naveda, K. C. Chang, David Hung-Chang Du. 696-701 [doi]
- A preprocessor for the via minimization problemK. C. Chang, David Hung-Chang Du. 702-707 [doi]
- Near-optimal ::::n::::-layer channel routingRichard J. Enbody, David Hung-Chang Du. 708-714 [doi]
- Principles of the SYCO compilerAhmed Amine Jerraya, P. Varinot, R. Jamier, Bernard Courtois. 715-721 [doi]
- DATAPATH: a CMOS data path silicon assemblerTom Marshburn, Ivy Lui, Rick Brown, Dan Cheung, Gary Lum, Peter Cheng. 722-729 [doi]
- An intelligent module generator environmentPaul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man. 730-735 [doi]
- HAPPI: a chip compiler based on double-level-metal technologyRathin Putatunda, David Smith, Stephen McNeary, James Crabbe. 736-743 [doi]
- An object-oriented, procedural database for VLSI chip planningWayne Wolf. 744-751 [doi]
- An automated database design tool using the ELKA conceptual modelJ. Gonzalez-Sustaeta, Alejandro P. Buchmann. 752-759 [doi]
- A delay test system for high speed logic LSI sKuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi. 786-790 [doi]
- Router system for printed wiring boards of very high-speed, very large-scale computersToshihiko Tada, Akihiko Hanafusa. 791-797 [doi]
- Hierarchical dynamic routerKaoru Kawamura, Masanobu Umeda, Hiroshi Shiraishi. 803-809 [doi]
- A parameter-driven routerVijay S. Bobba, J. W. Smith. 810-818 [doi]