Jayaram Bhasker - researchr alias

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Viewing Publication 1 - 14 from 14

2004

Improving Design and Verification Productivity with VHDL-200xStephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden. date 2004: 332-335 [doi]

1996

Die VHDL-SyntaxJayaram Bhasker. Markt und Technik, 1996.

1995

Datapath synthesis using a problem-space genetic algorithmMuhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker. tcad, 14(8):934-944, 1995. [doi]

1994

Size, chromatic number, and connectivityJayaram Bhasker, Tariq Samad, Douglas B. West. gc, 10(2-4):209-213, 1994. [doi]

1991

Simulation-Based Verification for High-Level SynthesisRolf Ernst, Jayaram Bhasker. dt, 8(1):14-20, 1991. [doi]

1990

An Optimizer for Hardware SynthesisJayaram Bhasker, Huan-Chih Lee. dt, 7(5):20-36, 1990. [doi]

1989

Via Assignment in Single-Row RoutingJayaram Bhasker, Sartaj Sahni. TC, 38(1):142-149, 1989.

1988

Process-graph Analyser: A Front-end Tool for VHDL Behavioural SynthesisJayaram Bhasker. SPE, 18(5):469-483, 1988.

Implementation of an optimizing compiler for VHDLJayaram Bhasker. SIGPLAN, 23(1):92-108, 1988. [doi]

A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated GraphJayaram Bhasker, Sartaj Sahni. algorithmica, 3:247-278, 1988.

1987

An algorithm for microcode compaction of VHDL behavioral descriptionsJayaram Bhasker. euromicro 1987: 54-58 [doi]

Compacting MIMOLA microcodeJayaram Bhasker, Tariq Samad. euromicro 1987: 97-105 [doi]

A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graphJayaram Bhasker, Sartaj Sahni. networks, 17(3):307-317, 1987. [doi]

1986

A linear algorithm to find a rectangular dual of a planar triangulated graphJayaram Bhasker, Sartaj Sahni. dac 1986: 108-114 [doi]

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