Table of Contents

• From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology DecisionsRobert C. Aitken, Fidel Muradali. 2
• Opportunities and Challenges in Building Silicon Products in 65nm and BeyondGreg Spirakis. 2-3 [doi]
• Systems on Chips Design: System Manufacturer Point of ViewVeikko Loukusa, Helena Pohjonen, Antti Ruha, Tarmo Ruotsalainen, Olli Varkki. 3-4 [doi]
• Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation TimesKihwan Choi, Ramakrishna Soma, Massoud Pedram. 4-9 [doi]
• Package Design for High Performance ICsSanjay Dandia. 5
• IP Testing - The Future Differentiator?Bill Eklow. 6-9 [doi]
• Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCsAdão Antônio de Souza Jr., Luigi Carro. 10-15 [doi]
• Hybrid Architectural Dynamic Thermal ManagementKevin Skadron. 10-15 [doi]
• Value-Conscious Cache: Simple Technique for Reducing Cache Access PowerYen-Jen Chang, Chia-Lin Yang, Feipei Lai. 16-21 [doi]
• RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-EndsFaress Tissafi-Drissi, Ian O Connor, Frédéric Gaffiot. 16-21 [doi]
• Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS TechnologyYiming Chen, Xiaojuen Yuan, David Scagnelli, James Mecke, Jeff Gross, David L. Harame. 22-27 [doi]
• State-Preserving vs. Non-State-Preserving Leakage Control in CachesYingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron. 22-29 [doi]
• Low Power Analogue 90 Degree Phase ShifterPeter H. Saul. 28-33 [doi]
• Arithmetic Reasoning in DPLL-Based SAT SolvingMarkus Wedler, Dominik Stoffel, Wolfgang Kunz. 30-35 [doi]
• A 16 Bit + Sign Monotonic Precise Current DAC for Sensor ApplicationsPavel Horsky. 34-38 [doi]
• Enhanced Diameter Bounding via StructuralJason Baumgartner, Andreas Kuehlmann. 36-41 [doi]
• An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design ChainSotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis. 39-45 [doi]
• Improved Symoblic Simulation by Dynamic Funtional Space PartitioningTao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin. 42-49 [doi]
• A High-Speed Transceiver Architecture Implementable as Synthesizable IP CoreAndreas Wortmann, Sven Simon, Matthias Müller. 46-51 [doi]
• Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay FaultsSaravanan Padmanaban, Spyros Tragoudas. 50-55 [doi]
• Design of Very Deep Pipelined Multipliers for FPGAsAlex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi. 52-57 [doi]
• Level of Similarity: A Metric for Fault CollapsingIrith Pomeranz, Sudhakar M. Reddy. 56-61 [doi]
• Application of a Multi-Processor SoC Platform to High-Speed Packet ForwardingPierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard. 58-63 [doi]
• Design of Routing-Constrained Low Power Scan ChainsYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 62-67 [doi]
• Islands of Synchronicity, a Design Methodology for SoC DesignA. P. Niranjan, Paul C. Wiscombe. 64-69 [doi]
• Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault DiagnosisIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri. 68-75 [doi]
• The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)Luigi Dadda, Marco Macchetti, Jeff Owen. 70-75 [doi]
• LZW-Based Code Compression for VLIW Embedded SystemsChang Hong Lin, Yuan Xie, Wayne Wolf. 76-81 [doi]
• A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed InputsAngelo Nagari, Germano Nicollini. 76-81 [doi]
• A Generic RTOS Model for Real-time Systems Simulation with SystemCRocco Le Moigne, Olivier Pasquier, Jean Paul Calvez. 82-87 [doi]
• Digital Background Gain Error Correction in Pipeline ADCsAntonio J. Ginés, Eduardo J. Peralías, Adoración Rueda. 82-87 [doi]
• Digital Ground Bounce Reduction by Phase Modulation of the ClockMustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 88-93 [doi]
• A Scalable Architecture for LDPC DecodinMauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken. 88-95 [doi]
• Pseudo-Random Sequence Based Tuning System for Continuous-Time FiltersFrancesco Corsi, Cristoforo Marzocca, Gianvito Matarrese, Andrea Baschirotto, Stefano D Amico. 94-101 [doi]
• Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping EnvironmentsStephen Schmitt, Wolfgang Rosenstiel. 96-101 [doi]
• A Crosstalk Aware Interconnect with Variable Cycle TransmissionLin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 102-107 [doi]
• Formal Refinement and Model Checking of an Echo Cancellation UnitAlexander Krupp, Wolfgang Müller 0003, Ian Oliver. 102-107 [doi]
• Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System ChipSandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk. 108-113 [doi]
• Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on ChipNattawut Thepayasuwan, Alex Doboli. 108-113 [doi]
• Have I Really Met Timing? - Validating PrimeTime Timing Reports with SpiceTobias Thiel. 114-119 [doi]
• Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control FlowSumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau. 114-121 [doi]
• At-Speed Testing of SOC ICsVlado Vorisek, Thomas Koch, Hermann Fischer. 120-125 [doi]
• SystemC and SystemVerilog: Where do They Fit? Where are They Going?Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji. 122-129 [doi]
• Utilizing Formal Assertions for System Design of Network ProcessorsXi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin. 126-133 [doi]
• Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction BusSiu-Kei Wong, Chi-Ying Tsui. 130-135 [doi]
• Clock Management in a Gigabit Ethernet Physical Layer Transceiver CircuitJuan C. Diaz, Marta Saburit. 134-139 [doi]
• Hierarchical Adaptive Dynamic Power ManagementZhiyuan Ren, Bruce H. Krogh, Radu Marculescu. 136-141 [doi]
• Expert System Perimeter Block Placement FloorplanningRichard Auletta. 140-143 [doi]
• A Self-Tuning Cache Architecture for Embedded SystemsChuanjun Zhang, Frank Vahid, Roman L. Lysecky. 142-147 [doi]
• A CAD Methodology and Tool for the Characterization of Wide On-Chip BusesIbrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, H. Smith. 144-149 [doi]
• Scheduling Reusable Instructions for Power ReductionJie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin. 148-155 [doi]
• MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] ModulatorsJesús Ruiz-Amaya, Josep Lluís de la Rosa, F. Medeiro, Francisco V. Fernández, Rocio del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez. 150-155 [doi]
• RTL Processor Synthesis for Architecture Exploration and ImplementationOliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl. 156-160 [doi]
• Using Counter Example Guided Abstraction Refinement to Find Complex BugsPer Bjesse, James H. Kukula. 156-161 [doi]
• Pattern Selection for Testing of Deep Sub-Micron Timing DefectsMango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng. 160 [doi]
• Java-through-C Compilation: An Enabling Technology for Java in Embedded SystemsAnkush Varma, Shuvra S. Bhattacharyya. 161-167 [doi]
• Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate CoprocessorKlaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey. 162-167 [doi]
• Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB RefinementsPanagiotis Manolios, Sudarshan K. Srinivasan. 168-175 [doi]
• Heterogeneous Co-Simulation of Networked Embedded SystemsFranco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla. 168-173 [doi]
• OCCN: A Network-On-Chip Modeling and Simulation FrameworkMarcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia, Francesco Papariello. 174-179 [doi]
• A Probabilistic Method for the Computation of Testability of RTL ConstructsJosé M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira. 176-181 [doi]
• A Design Methodology for the Exploitation of High Level Communication SynthesisFrancesco Bruschi, Massimo Bombana. 180-185 [doi]
• Graph-Based Functional Test Program Generation for Pipelined ProcessorsPrabhat Mishra, Nikil Dutt. 182-187 [doi]
• Software Processing Performance in Network ProcessorsIoannis Papaefstathiou, George Kornaros, Nicholaos Zervos. 186-191 [doi]
• Automatic Generation of Validation Stimuli for Application-Specific ProcessorsO. Goloubeva, Matteo Sonza Reorda, Massimo Violante. 188-193 [doi]
• Channel Decoder Architecture for 3G Mobile Wireless TerminalsFriedbert Berens, Gerd Kreiselmaier, Norbert Wehn. 192-197 [doi]
• Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering TechniquesMichael Dimopoulos, Panagiotis Linardis. 194-201 [doi]
• RASoC: A Router Soft-Core for Networks-on-ChipCesar Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin. 198-205 [doi]
• Data Reuse Analysis Technique for Software-Controlled Memory HierarchiesIlya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt. 202-207 [doi]
• Carry-Save Montgomery Modular Exponentiation on Reconfigurable HardwareAlessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese. 206-211 [doi]
• Automatic Tuning of Two-Level Caches to Embedded ApplicationsAnn Gordon-Ross, Frank Vahid, Nikil Dutt. 208-213 [doi]
• A CMOS-Based Tactile Sensor for Continuous Blood Pressure MonitoringKay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Andreas Hierlemann. 210-214 [doi]
• A CMOS-Based Tactile Sensor for Continuous Blood Pressure MonitoringKay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Andreas Hierlemann. 210-214 [doi]
• Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGAHala A. Farouk, Magdy Saeb. 212-217 [doi]
• Low Static-Power Frequent-Value Data CachesChuanjun Zhang, Jun Yang, Frank Vahid. 214-219 [doi]
• Optical Receiver IC for CD/DVD/Blue-Laser ApplicationJohannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann. 215-218 [doi]
• Optical Receiver IC for CD/DVD/Blue-Laser ApplicationJohannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann. 215-218 [doi]
• NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic DevicesDaniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael Canetti. 218-223 [doi]
• A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOSTerje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor. 219-222 [doi]
• A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOSTerje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor. 219-222 [doi]
• Using a Victim Buffer in an Application-Specific Memory HierarchyChuanjun Zhang, Frank Vahid. 220-227 [doi]
• A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. 223-226 [doi]
• A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. 223-226 [doi]
• Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA ImplementationRoger Endrigo Carvalho Porto, Luciano Volcan Agostini. 224-229 [doi]
• Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of StudyPaolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda. 228-233 [doi]
• Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of StudyPaolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda. 228-233 [doi]
• High Security SmartcardsMarc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain. 228-233 [doi]
• A Scalable Implementation of a Reconfigurable WCDMA Rake ReceiverMarc Quax, Jos Huisken, Jef L. van Meerbergen. 230-235 [doi]
• MultiNoC: A Multiprocessing System Enabled by a Network on ChipAline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes. 234-239 [doi]
• Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time ConstraintsJingcao Hu, Radu Marculescu. 234-239 [doi]
• MultiNoC: A Multiprocessing System Enabled by a Network on ChipAline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes. 234-239 [doi]
• Customisable EPIC Processor: Architecture and ToolsW. W. S. Chu, R. G. Dimond, S. Perrott, S. P. Seng, W. Luk. 236-241 [doi]
• Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nmDan Hillman. 240-246 [doi]
• A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die VariationsTom W. Chen, Justin Gregg. 240-245 [doi]
• Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nmDan Hillman. 240-246 [doi]
• A Run-Time Reconfigurable Datapath Architecture for Image Processing ApplicationsMarcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi. 242-247 [doi]
• A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA ImplementationKris Tiri, Ingrid Verbauwhede. 246-251 [doi]
• A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable PlatformsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. 247-252 [doi]
• A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable PlatformsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. 247-252 [doi]
• Synthesis of Embedded SystemC Design: A Case Study of Digital Neural NetworksDjones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel. 248-255 [doi]
• Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast ScalingWei-Chung Cheng, Yu Hou, Massoud Pedram. 252-259 [doi]
• Evaluation of SystemC Modelling of Reconfigurable Embedded SystemsTero Rissa, Adam Donlin, Wayne Luk. 253-258 [doi]
• Evaluation of SystemC Modelling of Reconfigurable Embedded SystemsTero Rissa, Adam Donlin, Wayne Luk. 253-258 [doi]
• Experiences during the Experimental Validation of the Time-Triggered ArchitectureSara Blanc, Joaquin Gracia, Pedro J. Gil. 256-261 [doi]
• Hardware Support for QoS-based Function Allocation in Reconfigurable SystemsMichael Ullmann, Wansheng Jin, Jürgen Becker. 259-264 [doi]
• Hardware Support for QoS-based Function Allocation in Reconfigurable SystemsMichael Ullmann, Wansheng Jin, Jürgen Becker. 259-264 [doi]
• Managing Don t Cares in Boolean SatisfiabilitySean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee. 260-265 [doi]
• Evaluation of a Refinement-Driven SystemC -Based Design FlowThorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel. 262-267 [doi]
• An Integrated Design and Verification Methodology for Reconfigurable Multimedia SystemsMichele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli. 266-271 [doi]
• Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of MicroprocessorsMiroslav N. Velev. 266-271 [doi]
• An Integrated Design and Verification Methodology for Reconfigurable Multimedia SystemsMichele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli. 266-271 [doi]
• Evaluation of an Object-Oriented Hardware Design Methodology for Automotive ApplicationsNico Bannow, Karsten Haug. 268-273 [doi]
• Common Reusable Verification Environment for BCA and RTL ModelsGiuseppe Falconeri, Walid Naifer, Nizar Romdhane. 272-277 [doi]
• A Novel SAT All-Solutions Solver for Efficient Preimage ComputationBin Li, Michael S. Hsiao, Shuo Sheng. 272-279 [doi]
• Common Reusable Verification Environment for BCA and RTL ModelsGiuseppe Falconeri, Walid Naifer, Nizar Romdhane. 272-277 [doi]
• The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-ChipW. J. Bainbridge, Luis A. Plana, Stephen B. Furber. 274-279 [doi]
• An Assembler Driven Verification Methodology (ADVM)John S. MacBeth, Dietmar Heinz, Ken Gray. 278-283 [doi]
• An Assembler Driven Verification Methodology (ADVM)John S. MacBeth, Dietmar Heinz, Ken Gray. 278-283 [doi]
• A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing ApplicationsBeibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai. 280-285 [doi]
• Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and BenefitGanesh Srinivasan, Soumendu Bhattacharya, Sasikumar Cherubal, Abhijit Chatterjee. 280-285 [doi]
• A Formal Verification Methodology for Checking Data IntegrityYasushi Umezawa, Takeshi Shimizu. 284-289 [doi]
• A Formal Verification Methodology for Checking Data IntegrityYasushi Umezawa, Takeshi Shimizu. 284-289 [doi]
• Random Jitter Extraction Technique in a Multi-Gigahertz SignalChee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang. 286-291 [doi]
• Qualification and Integration of Complex I/O in SoC Design FlowsJay Abraham, Guruprasad Rao. 286-293 [doi]
• On the Design and Verification Methodology of the Look-Aside InterfaceAli Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar. 290-295 [doi]
• On the Design and Verification Methodology of the Look-Aside InterfaceAli Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar. 290-295 [doi]
• Low Cost Analog Testing of RF Signal PathsMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 292-297 [doi]
• A Power Optimized Display Memory Organization for Handheld User TerminalLieven Hollevoet, Andy Dewilde, Kristof Denolf, Francky Catthoor, Filip Louagie. 294-299 [doi]
• A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test ApplicationsDiego Vázquez, Gildas Leger, Gloria Huertas, Adoración Rueda, José L. Huertas. 298-305 [doi]
• Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart CardsUlrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger. 300-305 [doi]
• Analysis and Modeling of Energy Reducing Source Code TransformationsCarlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto. 306-311 [doi]
• A Novel Implementation of Tile-Based Address MappingSambuddhi Hettiaratchi, Peter Y. K. Cheung. 306-311 [doi]
• A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip DesignFrancesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis. 312-317 [doi]
• Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory BanksZhong Wang, Xiaobo Sharon Hu. 312-317 [doi]
• Time-Energy Design Space Exploration for Multi-Layer Memory ArchitecturesRadoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski. 318-323 [doi]
• System Level Power Modeling and Simulation of High-End Industrial Network-on-ChipAndrea Bona, Vittorio Zaccaria, Roberto Zafalon. 318-323 [doi]
• Breaking Instance-Independent Symmetries in Exact Graph ColoringArathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 324-331 [doi]
• IEM926: An Energy Efficient SoC with Dynamic Voltage ScalingKrisztián Flautner, David Flynn, David Roberts, Dipesh I. Patel. 324-329 [doi]
• Can IP Quality be Objectively Measured?Kathy Werner. 330-331 [doi]
• How Can System-Level Design Solve the Interconnect Technology Scaling Problem?Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson. 332-339 [doi]
• Improving Design and Verification Productivity with VHDL-200xStephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden. 332-335 [doi]
• Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic ComponentsPierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa. 336-337 [doi]
• VHDL-AMS Library Development for Pacemaker ApplicationsB. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot. 338-341 [doi]
• System Design Using Kahn Process Networks: The Compaan/Laura ApproachTodor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere. 340-345 [doi]
• Modeling and Analysis of Heterogeneous Industrial Networks ArchitecturesFranco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino. 342-344
• Microarchitecture Development via Metropolis Successive Platform RefinementDouglas Densmore, Sanjay Rekhi, Alberto L. Sangiovanni-Vincentelli. 346-351 [doi]
• Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC DesignChulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo. 352-357 [doi]
• SoftContract: an Assertion-Based Software Development Process that Enables Design-by-ContractJean-Yves Brunel, Marco Di Natale, Alberto Ferrari, Paolo Giusto, Luciano Lavagno. 358-363 [doi]
• A System Level Exploration Platform and Methodology for Network Applications Based on Configurable ProcessorsD. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid. 364-371 [doi]
• Refinement of Mixed-Signal Systems with Affine ArithmeticChristoph Grimm, Wilhelm Heupke, Klaus Waldschmidt. 372-377 [doi]
• System-Level Performance Analysis in SystemCHector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco. 378-383 [doi]
• Modeling and Validating Globally Asynchronous Design in Synchronous FrameworksMohammad Reza Mousavi, Paul Le Guernic, Jean-Pierre Talpin, Sandeep K. Shukla, Twan Basten. 384-389 [doi]
• Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication ArchitecturesVijay D Silva, S. Ramesh, Arcot Sowmya. 390-395 [doi]
• Aspects of Formal and Graphical Design of a Bus SystemTiberiu Seceleanu, Tomi Westerlund. 396-403 [doi]
• Scan Power Minimization through Stimulus and Response TransformationsOzgur Sinanoglu, Alex Orailoglu. 404-409 [doi]
• Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?sMatthew W. Heath, Wayne P. Burleson, Ian G. Harris. 410-415 [doi]
• Wrapper Design for Testing IP Cores with Multiple Clock DomainsQiang Xu, Nicola Nicolici. 416-421 [doi]
• Efficient Modular Testing of SOCs Using Dual-Speed TAM ArchitecturesAnuja Sehgal, Krishnendu Chakrabarty. 422-427 [doi]
• An Arithmetic Structure for Test Data Horizontal CompressionMarie-Lise Flottes, Regis Poirier, Bruno Rouzeyre. 428-435 [doi]
• A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level DesignEwout Martens, Georges G. E. Gielen. 436-441 [doi]
• Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic TechniquesLutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke. 442-447 [doi]
• Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector MachinesTholom Kiely, Georges G. E. Gielen. 448-453 [doi]
• Extended Subspace Identification of Improper Linear SystemsGerd Vandersteen, Rik Pintelon, Dimitri Linten, Stéphane Donnay. 454-459 [doi]
• Identification and Modeling of Nonlinear Dynamic Behavior in Analog CircuitsXiaoling Huang, H. Alan Mantooth. 460-467 [doi]
• Exploring Logic Block Granularity for Regular FabricsAneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi. 468-473 [doi]
• Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable ArchitecturesNikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta. 474-479 [doi]
• A Configurable Logic Architecture for Dynamic Hardware/Software PartitioningRoman L. Lysecky, Frank Vahid. 480-485 [doi]
• Configuration-Sensitive Process Scheduling for FPGA-Based Computing PlatformsGuilin Chen, Mahmut T. Kandemir, Ugur Sezer. 486-493 [doi]
• Simultaneous State, Vt and Tox Assignment for Total Standby Power MinimizationDongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester. 494-499 [doi]
• A Scalable ODC-Based Algorithm for RTL Insertion of Gated ClocksPietro Babighian, Luca Benini, Enrico Macii. 500-505 [doi]
• Impact of Data Transformations on Memory Bank LocalityMahmut T. Kandemir. 506-511 [doi]
• Why Transition Coding for Power Minimization of On-Chip Buses Does Not WorkClaudia Kretzschmar, André K. Nieuwland, Dietmar Müller. 512-517 [doi]
• Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained SystemsAlexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi. 518-525 [doi]
• Dynamic Power Management Using Data BuffersLe Cai, Yung-Hsiang Lu. 526-531 [doi]
• Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network ApplicationsDavid Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris. 532-537 [doi]
• High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case StudyHye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim. 538-543 [doi]
• A SystemC-Based Verification Methodology for Complex Wireless Software IPGuido Post, P. K. Venkataraghavan, Tapan Ray, D. R. Seetharaman. 544-551 [doi]
• A New Optimized Implemention of the SystemC Engine Using Acyclic SchedulingDaniel Gracia Pérez, Gilles Mouchard, Olivier Temam. 552-557 [doi]
• Stimuli Generation with Late Binding of ValuesAvi Ziv. 558-563 [doi]
• Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoCFranco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino. 564-569 [doi]
• Extraction of Schematic Array Models for Memory CircuitsSoumitra Bose, Amit Nandi. 570-577 [doi]
• Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded ProcessorsAntonis M. Paschalis, Dimitris Gizopoulos. 578-583 [doi]
• Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGAM. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin. 584-589 [doi]
• Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global FlowRégis Leveugle, Abdelaziz Ammari. 590-595 [doi]
• On Concurrent Error Detection with Bounded Latency in FSMsSobeeh Almukhaizim, Petros Drineas, Yiorgos Makris. 596-603 [doi]
• Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance ModelsMukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen. 604-609 [doi]
• Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise AnalysisRajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori. 610-615 [doi]
• SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan LevelThomas Brandtner, Robert Weigel. 616-621 [doi]
• Optimization of Integrated Spiral Inductors Using Sequential Quadratic ProgrammingYong Zhan, Sachin S. Sapatnekar. 622-629 [doi]
• System Design for DSP Applications Using the MASIC MethodologyAbhijit K. Deb, Axel Jantsch, Johnny Öberg. 630-635 [doi]
• Flexible Software Protection Using Hardware/Software Codesign TechniquesJoseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari. 636-641 [doi]
• Interactive Cosimulation with Partial EvaluationPatrick Schaumont, Ingrid Verbauwhede. 642-647 [doi]
• Communication Analysis for System-On-Chip DesignAxel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel. 648-655 [doi]
• Extremely Low-Power LogicChristian Piguet, Jacques Gautier, Christoph Heer, Ian O Connor, Ulf Schlichtmann. 656-663 [doi]
• Decomposition of Instruction Decoder for Low Power DesignWu-An Kuo, TingTing Hwang, Allen C.-H. Wu. 664-665 [doi]
• Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex ProcessorsJohann Laurent, Nathalie Julien, Eric Senn, Eric Martin. 666-667 [doi]
• Formal Verification Coverage: Are the RTL-Properties Covering the Design s Architectural Intent?Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix. 668-669 [doi]
• Functional Coverage Metric Generation from Temporal Event Relation GraphYoung-Su Kwon, Chong-Min Kyung. 670-671 [doi]
• Automatic Scan Insertion and Pattern Generation for Asynchronous CircuitsAristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards. 672-673 [doi]
• Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] ModulatorsHassan Aboushady, L. de Lamarre, Nicolas Beilleau, Marie-Minerve Louërat. 674-675 [doi]
• A Methodology for System-Level Analog Design Space ExplorationFernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli. 676-677 [doi]
• Systematic Design for Optimization of High-Resolution Pipelined ADCsMohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei. 678-679 [doi]
• A Direct Bootstrapped CMOS Large Capacitive-Load Driver CircuitJosé C. García, Juan A. Montiel-Nelson, J. Sosa, Héctor Navarro. 680-681 [doi]
• Co-Processor Synthesis: A New Methodology for Embedded Software AccelerationBen I. Hounsell, Richard Taylor. 682-683 [doi]
• Behavioural Bitwise Scheduling Based on Computational Effort BalancingMaría C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida. 684-685 [doi]
• A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR FiltersAndrea Del Re, Alberto Nannarelli, Marco Re. 686-687 [doi]
• On Transfer Function and Power Consumption Transient ResponseLipeng Cao. 688-689 [doi]
• Polynomial Abstraction for Verification of Sequentially Implemented Combinational CircuitsTarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch. 690-691 [doi]
• Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon ValidationLi-C. Wang. 692-695 [doi]
• A Game Theoretic Approach to Low Energy Wireless Video StreamingAli Iranli, Kihwan Choi, Massoud Pedram. 696-697 [doi]
• Block-Enabled Memory Macros: Design Space Exploration and Application-Specific TuningLuca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii. 698-699 [doi]
• Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoCKimish Patel, Enrico Macii, Massimo Poncino. 700-701 [doi]
• A Low Power Strategy for Future Mobile TerminalsMladen Nikitovic, Mats Brorsson. 702-703 [doi]
• Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current AnalysisSwarup Bhunia, Arijit Raychowdhury, Kaushik Roy. 704-705 [doi]
• A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test PatternsLuís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur. 706-707 [doi]
• A Digital Test for First-Order [Sigma-Delta] ModulatorsGildas Leger, Adoración Rueda. 708-709 [doi]
• SoC Test Scheduling with Power-Time Tradeoff and Hot Spot AvoidanceJames Chin, Mehrdad Nourani. 710-711 [doi]
• STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP CoresMounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna. 712-713 [doi]
• Are Our Design for Testability Features Fault Secure?Cecilia Metra, T. M. Mak, Martin Omaña. 714-715 [doi]
• Test Compression and Hardware Decompression for Scan-Based SoCsFrancis G. Wolff, Christos A. Papachristou, David R. McIntyre. 716-717 [doi]
• Concurrent Sizing, Vdd and Vth Assignment for Low-Power DesignAshish Srivastava, Dennis Sylvester, David Blaauw. 718-719 [doi]
• Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-GatingPietro Babighian, Luca Benini, Enrico Macii. 720-723 [doi]
• An Asynchronous Synthesis Toolset Using VerilogFrank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev. 724-725 [doi]
• Organizing Libraries of DFG PatternsGero Dittmann. 726-727 [doi]
• Compositional Memory Systems for Data Intensive ApplicationsAnca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven. 728-729 [doi]
• Scalar Metric for Temporal Locality and Estimation of Cache PerformanceJuha Alakarhu, Jarkko Niittylahti. 730-731 [doi]
• .NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and SimulationJames Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois. 732-733 [doi]
• Modeling and Simulating Memory Hierarchies in a Platform-Based Design MethodologyPablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo. 734-735 [doi]
• Integrating the Synchronous Dataflow Model with UMLPeter Green, Salah Essa. 736-737 [doi]
• Design and Behavioral Modeling Tools for Optical Network-on-ChipMatthieu Briere, L. Carrel, T. Michalke, Fabien Mieyeville, Ian O Connor, Frédéric Gaffiot. 738-739 [doi]
• Hierarchical Modeling and Simulation of Large Analog CircuitsSheldon X.-D. Tan, Zhenyu Qi, Hang Li. 740-741 [doi]
• Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMSPeter R. Wilson, J. Neil Ross, Andrew D. Brown, Tom J. Kazmierski, Jerzy Baranowski. 742-743 [doi]
• A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA PlacementManish Handa, Ranga Vemuri. 744-745 [doi]
• Enhancing Reliability of Operational Interconnections in FPGAsAlex Fit-Florea, Miroslav Halas, Fatih Kocan. 746-747 [doi]
• Operating System Support for Interface Virtualisation of Reconfigurable CoprocessorsMiljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne. 748 [doi]
• Analyzing On-Chip Communication in a MPSoC EnvironmentMirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon. 752-757 [doi]
• A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCMatthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert. 758-763 [doi]
• Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based ApproachSantiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal. 764-769 [doi]
• A Case Study in Networks-on-Chip Design for Embedded VideoJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv. 770-777 [doi]
• Exploiting Crosstalk to Speed up On-Chip BuseChunjie Duan, Sunil P. Khatri. 778-783 [doi]
• False-Noise Analysis for Domino CircuitsAlexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer. 784-789 [doi]
• Crosstalk Minimization in Logic Synthesis for PLAYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang. 790-795 [doi]
• Synthesis for Manufacturability: A Sanity CheckAlessandra Nardi, Alberto L. Sangiovanni-Vincentelli. 796-803 [doi]
• Design of Sub-10-Picoseconds On-Chip Time Measurement CircuitM. A. Abas, Gordon Russell, D. J. Kinniment. 804-809 [doi]
• Impact of Test Point Insertion on Silicon Area and Timing during LayoutHarald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich. 810-815 [doi]
• Designing Self Test Programs for Embedded DSP CoresHani Rizk, Christos A. Papachristou, Francis G. Wolff. 816-823 [doi]
• Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise PredictionZhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury. 824-829 [doi]
• Thermal and Power Integrity Based Power/Ground Networks OptimizationTing-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen. 830-835 [doi]
• Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICsHai Lan, Robert W. Dutton. 836-843 [doi]
• DATE Panel: Chips of the Future: Soft, Crunchy or Hard?Pierre G. Paulin. 844-851 [doi]
• Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor NetworksIsmail Kadayif, Mahmut T. Kandemir. 852-857 [doi]
• Power-Aware Network Swapping for Wireless Palmtop PCsAndrea Acquaviva, Emanuele Lattanzi, Alessandro Bogliolo. 858-863 [doi]
• Power Aware Interface Synthesis for Bus-Based SoC DesignNikolaos D. Liveris, Prithviraj Banerjee. 864-869 [doi]
• Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous OnesAlex Branover, Rakefet Kol, Ran Ginosar. 870-877 [doi]
• An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network ConfigurationAndrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage. 878-883 [doi]
• ×pipesCompiler: A Tool for Instantiating Application Specific Networks on ChipAntoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 884-889 [doi]
• Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on ChipMikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch. 890-895 [doi]
• Bandwidth-Constrained Mapping of Cores onto NoC ArchitecturesSrinivasan Murali, Giovanni De Micheli. 896-903 [doi]
• Synthesis and Optimization of Threshold Logic Networks with Application to NanotechnologiesRui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha. 904-909 [doi]
• Fast Comparisons of Circuit ImplementationsShrirang K. Karandikar, Sachin S. Sapatnekar. 910-915 [doi]
• Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAsAnurag Tiwari, Karen A. Tomko. 916-921 [doi]
• MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence AnalysisA. Manoj Kumar, Jayaram Bobba, V. Kamakoti. 922-929 [doi]
• Nanometer Design: What are the Requirements for Manufacturing Test?Janusz Rajski, Kan Thapar. 930-937 [doi]
• Poor Man s TBR: A Simple Model Reduction SchemeJoel R. Phillips, Luis Miguel Silveira. 938-943 [doi]
• Model Order Reduction Techniques for Linear Systems with Large Numbers of TerminalsPeter Feldmann. 944-947 [doi]
• SCORE: SPICE COmpatible Reluctance ExtractionRong Jiang, Charlie Chung-Ping Chen. 948-953 [doi]
• A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including CrosstalkJosé Luis Rosselló, Jaume Segura. 954-961 [doi]
• A Framework for Battery-Aware Sensor ManagementSridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan. 962-967 [doi]
• Local Decisions and Triggering Mechanisms for Adaptive Fault-TolerancePhillip Stanley-Marbell, Diana Marculescu. 968-973 [doi]
• An Algorithm for Nano-Pipelining of Circuits and Architectures for a NanotechnologyPallav Gupta, Niraj K. Jha. 974-979 [doi]
• Smaller Two-Qubit Circuits for Quantum Communication and ComputationVivek V. Shende, Igor L. Markov, Stephen S. Bullock. 980-987 [doi]
• Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia ProcessingIngrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis. 988-995 [doi]
• Measurement of IP Qualification Costs and BenefitsAndreas Vörg, Martin Radetzki, Wolfgang Rosenstiel. 996-1001 [doi]
• Architecture-Level Performance Estimation for IP-Based Embedded SystemsKyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 1002-1007 [doi]
• Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock ArchitecturesMontek Singh, Michael Theobald. 1008-1013 [doi]
• Platform Based on Open-Source Cores for Industrial ApplicationsM. Bolado, Hector Posadas, Javier Castillo, P. Huerta, Pablo Sánchez, C. Sánchez, H. Fouren, Francisco Blasco. 1014-1019 [doi]
• MINCE: Matching INstructions Using Combinational Equivalence for Extensible ProcessorNewton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan. 1020-1027 [doi]
• Design Optimization of Multi-Cluster Embedded Systems for Real-Time ApplicationPaul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal. 1027-1033 [doi]
• Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with CachesYudong Tan, Vincent John Mooney III. 1034-1039 [doi]
• Workload Characterization Model for Tasks with Variable Execution DemandAlexander Maxiaguine, Simon Künzli, Lothar Thiele. 1040-1045 [doi]
• Context-Aware Performance Analysis for Efficient Embedded System DesignMarek Jersak, Rafik Henia, Rolf Ernst. 1046-1051 [doi]
• Compact Binaries with Code Compression in a Software Dynamic TranslatorStacey Shogan, Bruce R. Childers. 1052-1059 [doi]
• Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic DefectsJennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer. 1066-1071 [doi]
• Intermittent Scan Chain Fault Diagnosis Based on Signal Probability AnalysisYu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung. 1072-1077 [doi]
• A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated CircuitChandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang. 1078-1083 [doi]
• Soft Faults and the Importance of Stresses in Memory TestingZaid Al-Ars, A. J. van de Goor. 1084-1091 [doi]
• Wire Retiming for System-on-Chip by Fixpoint ComputationChuan Lin, Hai Zhou. 1092-1097 [doi]
• Boosting: Min-Cut Placement with Improved Signal DelayAndrew B. Kahng, Igor L. Markov, Sherief Reda. 1098-1103 [doi]
• Optimal Algorithm for Minimizing the Number of Twists in an On-Chip BusLiang Deng, Martin D. F. Wong. 1104-1109 [doi]
• A Fast Word-Level Statistical Estimator of Intra-Bus CrosstalkSuvodeep Gupta, Srinivas Katkoori. 1110-1115 [doi]
• Full-Chip Multilevel Routing for Power and Signal IntegrityJinjun Xiong, Lei He. 1116-1123 [doi]
• Energy-Aware System Design for Wireless MultimediaHans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau. 1124-1131 [doi]
• Unified Component Integration Flow for Multi-Processor SoC Design and ValidationMohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya. 1132-1137 [doi]
• An Interconnect Channel Design Methodology for High Performance Integrated CircuitsVikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi. 1138-1143 [doi]
• Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical ApproachAlex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas. 1144-1149 [doi]
• Supporting Cache Coherence in Heterogeneous Multiprocessor SystemsTaeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee. 1150-1157 [doi]
• Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip MultiprocessorsIsmail Kadayif, Mahmut T. Kandemir, Ibrahim Kolcu. 1158-1163 [doi]
• Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control ApplicationsClaudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 1164-1169 [doi]
• Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded SystemsYing Zhang, Krishnendu Chakrabarty. 1170-1175 [doi]
• Quasi-Static Scheduling for Real-Time Systems with Hard and Soft TasksLuis Alejandro Cortés, Petru Eles, Zebo Peng. 1176-1183 [doi]
• Status of IEEE Testability Standards 1149.4, 1532 and 1149.6Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts. 1184-1191 [doi]
• Eliminating False Positives in Crosstalk Noise AnalysisYajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska. 1192-1197 [doi]
• A New Approach to Timing Analysis Using Event Propagation and Temporal LogicArijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal. 1198-1203 [doi]
• A New Effective Congestion Model in Floorplan DesignYi-Lin Hsieh, Tsai-Ming Hsieh. 1204-1209 [doi]
• ULSI Interconnect Length Distribution Model Considering Core UtilizationHidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu. 1210-1217 [doi]
• Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable PlatformAlberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno. 1218-1223 [doi]
• Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case StudyBingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins. 1224-1229 [doi]
• Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable ArraysSami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed, Nizamettin Aydin, Tughrul Arslan, Fred Westall. 1230-1235 [doi]
• Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and ExperienceHelena Krupnova. 1236-1243 [doi]
• Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for MultiprocessingXinping Zhu, Sharad Malik. 1244-1249 [doi]
• A Power and Performance Model for Network-on-Chip ArchitecturesNilanjan Banerjee, Praveen Vellanki, Karam S. Chatha. 1250-1255 [doi]
• A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip PlatformAndreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl. 1256-1263 [doi]
• Cache-Aware Scratchpad Allocation AlgorithmManish Verma, Lars Wehmeyer, Peter Marwedel. 1264-1269 [doi]
• Phase Coupled Code Generation for DSPs Using a Genetic AlgorithmMarkus Lorenz, Peter Marwedel. 1270-1275 [doi]
• A Methodology and Tool Suite for C Compiler Generation from ADL Processor ModelsManuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren. 1276-1283 [doi]
• Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip DecompressionMohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty. 1284-1289 [doi]
• CircularScan: A Scan Architecture for Test Cost ReductionBaris Arslan, Alex Orailoglu. 1290-1295 [doi]
• Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test SetsSeongmoon Wang, Xiao Liu, Srimat T. Chakradhar. 1296-1301 [doi]
• Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting CodeAndreas Leininger, Michael Gössel, Peter Muhmenthaler. 1302-1309 [doi]
• Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit SimulationBo Wan, C.-J. Richard Shi. 1310-1315 [doi]
• Direct Nonlinear Order Reduction with Variational AnalysisLihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang. 1316-1321 [doi]
• Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution MethodXin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang. 1322-1326 [doi]
• Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed CircuitsTakashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. 1327-1333 [doi]
• System Verilog for VHDL UsersTom Fitzpatric. 1334-1341 [doi]
• Distributed Multimedia System Design: A Holistic PerspectiveRadu Marculescu, Massoud Pedram, Jörg Henkel. 1342-1349 [doi]
• Adaptive Prefetching for Multimedia Applications in Embedded SystemsHassan Sbeyti, Smaïl Niar, Lieven Eeckhout. 1350-1351 [doi]
• Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident DatabasesJayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir. 1352-1353 [doi]
• High-Performance QuIDD-Based Simulation of Quantum CircuitsGeorge F. Viamontes, Igor L. Markov, John P. Hayes. 1354-1355 [doi]
• An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System SimulationD. K. Reed, Steven P. Levitan, J. Boles, Jose A. Martinez, Donald M. Chiarulli. 1356-1357 [doi]
• Fault Tolerance of Programmable Switch BlocksJing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi. 1358-1359 [doi]
• A New Self-Checking Sum-Bit Duplicated Carry-Select AdderEgor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel. 1360-1361 [doi]
• A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise GenerationLuis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González. 1362-1363 [doi]
• Accurate Estimation of Parasitic Capacitances in Analog CircuitsAnuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri. 1364-1365 [doi]
• GRAAL - A Development Framework for Embedded Graphics AcceleratorsDan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha. 1366-1367 [doi]
• From Synchronous to Asynchronous: An Automatic ApproachJordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou. 1368-1369 [doi]
• Enhancing Testability of System on Chips Using Network Management ProtocolsOussama Laouamri, Chouki Aktouf. 1370-1371 [doi]
• Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert TechniqueMatheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger. 1372-1373 [doi]
• Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded ProcessorsJuan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu. 1374-1375 [doi]
• Dynamic Voltage and Cache Reconfiguration for Low PowerAndré C. Nácul, Tony Givargis. 1376-1379 [doi]
• Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented ModelsMaziar Goudarzi, Shaahin Hessabi, Alan Mycroft. 1380-1381 [doi]
• Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent SoftwareSungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava. 1382-1383 [doi]
• Synthesis of Reversible LogicAbhinav Agrawal, Niraj K. Jha. 1384-1385 [doi]
• A Unified Design Space for Regular Parallel Prefix AddersMatthew M. Ziegler, Mircea R. Stan. 1386-1387 [doi]
• MODD: A New Decision Diagram and Representation for Multiple Output Binary FunctionsAbusaleh M. Jabir, Dhiraj K. Pradhan. 1388-1389 [doi]
• Issues in Implementing Latency Insensitive ProtocolsMario R. Casu, Luca Macchiarulo. 1390-1391 [doi]
• Model-Based Specification and Execution of Embedded Real-Time SystemsTim Schattkowsky, Wolfgang Müller 0003. 1392-1393 [doi]
• A Demonstration of Co-Design and Co-Verification in a Synchronous LanguageSatnam Singh. 1394-1395 [doi]
• Profile Guided Management of Code Partitions for Embedded SystemsShukang Zhou, Bruce R. Childers, Naveen Kumar. 1396-1399 [doi]
• Realizable Reduction for Electromagnetically Coupled RLMC InterconnectsRong Jiang, Charlie Chung-Ping Chen. 1400-1401 [doi]
• Statistically Aware Buffer PlanningGiuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten. 1402-1403 [doi]
• A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron TechnologyS. Bernardini, Jean Michel Portal, Pascal Masson. 1404-1405 [doi]
• Power Supply Noise Monitor for Signal Integrity FaultsJosep Rius Vázquez, José Pineda de Gyvez. 1406-1407 [doi]
• Testing of Quantum Dot Cellular Automata Based DesignsMehdi Baradaran Tahoori, Fabrizio Lombardi. 1408-1409 [doi]
• Net and Pin Distribution for 3D Package Global RoutingJacob R. Minz, Mohit Pathak, Sung Kyu Lim. 1410-1411 [doi]
• Placement Using a Localization Probability Model (LPM)Markus Olbrich, Erich Barke. 1412 [doi]
• CMOS Structures Suitable for Secured HardwareSylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost. 1414-1415 [doi]
• Timing Correction and Optimization with Adaptive Delay Sequential ElementKambiz Rahimi, Seth Bridges, Chris Diorio. 1416 [doi]