Keishi Sakanushi - researchr alias

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Viewing Publication 1 - 35 from 35

2013

Electronic triage system for continuously monitoring casualties at disaster scenesKeishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka. jaihc, 4(5):547-558, 2013. [doi]

2012

2011

Biological information sensing technologies for medical, health care, and wellness applicationsMasaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato. aspdac 2011: 551-555 [doi]

Electronic Triage System: Casualties Monitoring System in the Disaster SceneKeishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka. 3pgcic 2011: 317-322 [doi]

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder DesignIttetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. ieicet, 94-A(12):2659-2668, 2011. [doi]

Automated architecture exploration for low energy reconfigurable AGUIttetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. isocc 2011: 191-194 [doi]

2010

2009

2007

A low power VLIW processor generation method by means of extracting non-redundant activation conditionsHirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. codes 2007: 227-232 [doi]

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional UnitsTakeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. aspdac 2007: 286-291 [doi]

A Block-Floating-Point Processor for Rapid Application DevelopmentHiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi. icassp 2007: 65-68 [doi]

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision DiagramHiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto. ieicet, 90-A(12):2800-2809, 2007. [doi]

2006

2005

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemCM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. date 2005: 554-559 [doi]

Enabling RTOS simulation modeling in a system level design languageM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. aspdac 2005: 936-939 [doi]

2004

2003

2002

Recognition of Floorplan by Parametric BSG for Reuse of Layout DesignKeishi Sakanushi, Zhonglin Wu, Yoji Kajitani. ieiceta, 85-A(4):872-879, 2002. [doi]

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis TreesChangwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin. date 2002: 61-68 [doi]

1998

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applicationsShigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita. iccad 1998: 418-425 [doi]

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocksKeishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani. iccad 1998: 267-274 [doi]

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