Abstract is missing.
- Embedded memories in system design - from technology to systems architectureSoren Hein, Vijay Nagasamy, Bernhard Rohfleisch, Christoforos E. Kozyrakis, Nikil D. Dutt, Francky Catthoor. 1 [doi]
- Real-time operating systems for embedded computingSerge Hustin, Miodrag Potkonjak, Eric Verhulst, Wayne Wolf. 2 [doi]
- High-level design validation and testSujit Dey, Jacob A. Abraham, Yervant Zorian. 3 [doi]
- Interconnect in high speed designs: problems, methodologies and toolsPhillip Restle, Joel R. Phillips, Ibrahim M. Elfadel. 4 [doi]
- How will CAD handle billion-transistor systems? (panel)Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf. 5 [doi]
- Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstressTong Li, Ching-Han Tsai, Sung-Mo Kang. 6-11 [doi]
- Simulation of coupling capacitances using matrix partitioningTuyen V. Nguyen, Anirudh Devgan, Ali Sadigh. 12-18 [doi]
- h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous responseTao Lin, Emrah Acar, Lawrence T. Pileggi. 19-25 [doi]
- Wireplanning in logic synthesisWilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 26-33 [doi]
- Graph matching-based algorithms for FPGA segmentation designYao-Wen Chang, Jai-Ming Lin, D. F. Wong. 34-39 [doi]
- Delay-oriented technology mapping for heterogeneous FPGAs with bounded resourcesJason Cong, Songjie Xu. 40-44 [doi]
- Control generation for embedded systems based on composition of modal processesPai H. Chou, Ken Hines, Kurt Partridge, Gaetano Borriello. 46-53 [doi]
- Representation of process mode correlation for schedulingDirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele. 54-61 [doi]
- CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systemsRobert P. Dick, Niraj K. Jha. 62-67 [doi]
- Synthesis of BIST hardware for performance testing of MCM interconnectionsRajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian. 69-73 [doi]
- Using a single input to support multiple scan chainsKuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang. 74-78 [doi]
- High-level variable selection for partial-scan implementationFrank F. Hsu, Janak H. Patel. 79-84 [doi]
- Multipoint moment matching model for multiport distributed interconnect networksQingjian Yu, Janet Meiling Wang, Ernest S. Kuh. 85-91 [doi]
- Reduced-order modelling of linear time-varying systemsJaijeet S. Roychowdhury. 92-95 [doi]
- Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectorsJoel R. Phillips. 96-102 [doi]
- Implementation and use of SPFDs in optimizing Boolean networksSubarnarekha Sinha, Robert K. Brayton. 103-110 [doi]
- Finding all simple disjunctive decompositions using irredundant sum-of-products formsShin-ichi Minato, Giovanni De Micheli. 111-117 [doi]
- On accelerating pattern matching for technology mappingYusuke Matsunaga. 118-122 [doi]
- A performance-driven layer assignment algorithm for multiple interconnect treesPrashant Saxena, C. L. Liu. 124-127 [doi]
- Optimal 2-D cell layout with integrated transistor foldingAvaneendra Gupta, John P. Hayes. 128-135 [doi]
- Integrating logic retiming and register placementTzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin. 136-139 [doi]
- Static compaction using overlapped restoration and segment pruningSurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy. 140-146 [doi]
- Dynamic fault collapsing and diagnostic test pattern generation for sequential circuitsVamsi Boppana, W. Kent Fuchs. 147-154 [doi]
- Phase noise in oscillators: DAEs and colored noise sourcesAlper Demir. 170-177 [doi]
- High-order Nyström schemes for efficient 3-D capacitance extractionSharad Kapur, David E. Long. 178-185 [doi]
- Signature hiding techniques for FPGA intellectual property protectionJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 186-189 [doi]
- Analysis of watermarking techniques for graph coloring problemGang Qu, Miodrag Potkonjak. 190-193 [doi]
- Intellectual property protection by watermarking combinational logic synthesis solutionsDarko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong. 194-198 [doi]
- Estimating noise in RF systemsJaijeet S. Roychowdhury, Alper Demir. 199-202 [doi]
- Getting to the bottom of deep submicronDennis Sylvester, Kurt Keutzer. 203-211 [doi]
- Determination of worst-case aggressor alignment for delay calculationPaul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi. 212-219 [doi]
- Noise considerations in circuit optimizationAndrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah. 220-227 [doi]
- Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuitsFabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi. 235-241 [doi]
- Domino logic synthesis using complex static gatesTyler Thorp, Gin Yee, Carl Sechen. 242-247 [doi]
- Technology mapping for domino logicMin Zhao, Sachin S. Sapatnekar. 248-251 [doi]
- Slicing floorplans with pre-placed modulesFung Yu Young, D. F. Wong. 252-258 [doi]
- Arbitrary rectilinear block packing based on sequence pairMaggie Zhiwei Kang, Wayne Wei-Ming Dai. 259-266 [doi]
- The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocksKeishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani. 267-274 [doi]
- On primitive fault test generation in non-scan sequential circuitsRamesh C. Tekumalla, Premachandran R. Menon. 275-282 [doi]
- Test set compaction algorithms for combinational circuitsIlker Hamzaoglu, Janak H. Patel. 283-289 [doi]
- A linear optimal test generation algorithm for interconnect testingChauchin Su. 290-295 [doi]
- GPCAD: a tool for CMOS op-amp synthesisMaria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee. 296-303 [doi]
- An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuitsFrancky Leyn, Georges G. E. Gielen, Willy M. C. Sansen. 304-307 [doi]
- Efficient analog circuit synthesis with simultaneous yield and robustness optimizationGeert Debyser, Georges G. E. Gielen. 308-311 [doi]
- Reencoding for cycle-time minimization under fixed encoding lengthBalakrishnan Iyer, Maciej J. Ciesielski. 312-315 [doi]
- Using precomputation in architecture and logic resynthesisSoha Hassoun, Carl Ebeling. 316-323 [doi]
- Lazy transition systems: application to timing optimization of asynchronous circuitsJordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev. 324-331 [doi]
- A general approach for regularity extraction in datapath circuitsAmit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta. 332-339 [doi]
- SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from CLuc Séméria, Giovanni De Micheli. 340-346 [doi]
- A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesisChunho Lee, Miodrag Potkonjak. 347-351 [doi]
- Approximate reachability don t cares for CTL model checkingIn-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley. 351-358 [doi]
- Adaptive variable reordering for symbolic model checkingGila Kamhi, Limor Fix. 359-365 [doi]
- Verification by approximate forward and backward reachabilityShankar G. Govindaraju, David L. Dill. 366-370 [doi]
- Waiting false path analysis of sequential logic circuits for performance optimizationKazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe. 392-395 [doi]
- Asymptotically efficient retiming under setup and hold constraintsMarios C. Papaefthymiou. 396-401 [doi]
- On the optimization power of retiming and resynthesis transformationsRajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton. 402-407 [doi]
- Architecture driven circuit partitioningChau-Shen Chen, TingTing Hwang, C. L. Liu. 408-411 [doi]
- Integrating floorplanning in data-transfer based high-level synthesisShantanu Tarafdar, Miriam Leeser, Zixin Yin. 412-417 [doi]
- The channeled-BSG: a universal floorplan for simultaneous place/route with IC applicationsShigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita. 418-425 [doi]
- A graph-partitioning-based approach for multi-layer constrained via minimizationYih-Chih Chou, Youn-Long Lin. 426-429 [doi]
- Hardware/software co-synthesis with memory hierarchiesYanbing Li, Wayne Wolf. 430-436 [doi]
- Communication synthesis for distributed embedded systemsRoss B. Ortega, Gaetano Borriello. 437-444 [doi]
- Analysis of emerging core-based design lifecycleKayhan Küçükçakar. 445-449 [doi]
- Core integration: overview and challengesEnno Wein. 450-452 [doi]
- Full-chip verification of UDSM designsResve A. Saleh, David Overhauser, Sandy Taylor. 453-460 [doi]
- Node sampling: a robust RTL power modeling approachAlessandro Bogliolo, Luca Benini. 461-467 [doi]
- Estimation of power sensitivity in sequential circuits with power macromodeling applicationZhanping Chen, Kaushik Roy, Edwin K. P. Chong. 468-472 [doi]
- Power invariant vector sequence compactionAli Pinar, C. L. Liu. 473-476 [doi]
- Efficient encoding for exact symbolic automata-based schedulingSteve Haynal, Forrest Brewer. 477-481 [doi]
- A new algorithm for the reduction of incompletely specified finite state machinesJorge M. Pena, Arlindo L. Oliveira. 482-489 [doi]
- Static power optimization of deep submicron CMOS circuits for dual VT technologyQi Wang, Sarma B. K. Vrudhula. 490-496 [doi]
- Network flow based circuit partitioning for time-multiplexed FPGAsHuiqun Liu, D. F. Wong. 497-504 [doi]
- On multilevel circuit partitioningSverre Wichlund. 505-511 [doi]
- Multiway partitioning with pairwise movementJason Cong, Sung Kyu Lim. 512-516 [doi]
- Verification of RTL generated from scheduled behavior in a high-level synthesis flowPranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama. 517-524 [doi]
- Functional debugging of systems-on-chipDarko Kirovski, Miodrag Potkonjak, Lisa M. Guerra. 525-528 [doi]
- Formal verification of pipeline control using controlled token nets and abstract interpretationPei-Hsin Ho, Adrian J. Isles, Timothy Kam. 529-536 [doi]
- Proposal of a timing model for CMOS logic gates driving a CRC loadAkio Hirata, Hidetoshi Onodera, Keikichi Tamaru. 537-544 [doi]
- Gate-size selection for standard cell librariesFrederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok. 545-550 [doi]
- Fanout optimization under a submicron transistor-level delay modelPasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni. 551-556 [doi]
- Efficient equivalence checking of multi-phase designs using retimingGagan Hasteer, Anmol Mathur, Prithviraj Banerjee. 557-562 [doi]
- Robust latch mapping for combinational equivalence checkingJerry R. Burch, Vigyan Singhal. 563-569 [doi]
- Tight integration of combinational verification methodsJerry R. Burch, Vigyan Singhal. 570-576 [doi]
- Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptionsSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. 577-584 [doi]
- Period assignment in multidimensional periodic schedulingWim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp. 585-592 [doi]
- Improving the computational performance of ILP-based problemsM. Narasimhan, J. Ramanujam. 593-596 [doi]
- Techniques for energy minimization of communication pipelinesGang Qu, Miodrag Potkonjak. 597-600 [doi]
- PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsisSumit Roy, Harm Arts, Prithviraj Banerjee. 601-606 [doi]
- Accurate calculation of bit-level transition activity using word-level statistics and entropy functionEfstathios D. Kyriakis-Bitzaros, Spiridon Nikolaidis, Anna Tatsaki. 607-610 [doi]
- Shaping a VLSI wire to minimize delay using transmission line modelYouxin Gao, D. F. Wong. 611-616 [doi]
- Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationChung-Ping Chen, Chris C. N. Chu, D. F. Wong. 617-624 [doi]
- A simultaneous routing tree construction and fanout optimization algorithmAmir H. Salek, Jinan Lou, Massoud Pedram. 625-630 [doi]
- Sampling schemes for computing OBDD variable orderingsJawahar Jain, William Adams, Masahiro Fujita. 631-638 [doi]
- The design of a cache-friendly BDD libraryDavid E. Long. 639-645 [doi]
- Design of experiments in BDD variable ordering: lessons learnedJustin E. Harlow III, Franc Brglez. 646-652 [doi]
- On-line scheduling of hard real-time tasks on variable voltage processorInki Hong, Miodrag Potkonjak, Mani B. Srivastava. 653-656 [doi]
- Transforming control-flow intensive designs to facilitate power managementGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. 657-664 [doi]
- Synthesis of application specific instructions for embedded DSP softwareHoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park. 665-671 [doi]
- Word-level decision diagrams, WLCDs and divisionChristoph Scholl, Bernd Becker, Thomas M. Weis. 672-677 [doi]
- Symbolic model checking of process networks using interval diagram techniquesKarsten Strehl, Lothar Thiele. 686-692 [doi]
- Interface synthesis: a vertical slice from digital logic to software componentsGaetano Borriello, Luciano Lavagno, Ross B. Ortega. 693-695 [doi]
- Dynamic power management of electronic systemsLuca Benini, Alessandro Bogliolo, Giovanni De Micheli. 696-702 [doi]