Gin Yee - researchr alias

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Viewing Publication 1 - 10 from 10

2002

Locally clocked pipelines and dynamic logicG. N. Hoyer, Gin Yee, Carl Sechen. tvlsi, 10(1):58-62, 2002. [doi]

2000

Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino LogicJovanka Ciric, Gin Yee, Carl Sechen. date 2000: 277-282 [doi]

Output Prediction Logic: A High-Performance CMOS Design TechniqueLarry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen. iccd 2000: 247 [doi]

Clock-delayed domino for dynamic circuit designGin Yee, Carl Sechen. tvlsi, 8(4):425-430, 2000. [doi]

An Automated Shielding Algorithm and Tool For Dynamic CircuitsGin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen. isqed 2000: 369-374 [doi]

1999

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processorsFabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee. jssc, 34(5):712-716, 1999. [doi]

Design and Synthesis of Monotonic CircuitsTyler Thorp, Gin Yee, Carl Sechen. iccd 1999: 569-572 [doi]

1998

Domino logic synthesis using complex static gatesTyler Thorp, Gin Yee, Carl Sechen. iccad 1998: 242-247 [doi]

1996

Clock-Delayed Domino for Adder and Combinational Logic DesigGin Yee, Carl Sechen. iccd 1996: 332 [doi]

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