Table of Contents

• Enhancing FSM Traversal by Temporary Re-EncodingGianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich. 6-11 [doi]
• Early Quantification and Partitioned Transition RelationsRamin Hojati, Sriram C. Krishnan, Robert K. Brayton. 12-19 [doi]
• Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State EnumerationMichel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny. 20-26 [doi]
• Boolean Function Representation Based on Disjoint-Support DecompositionsValeria Bertacco, Maurizio Damiani. 27 [doi]
• A multiseed counter TPG with performance guaranteeDimitrios Kagaris, Spyros Tragoudas. 34-39 [doi]
• Design for testability of integrated operational amplifiers using oscillation-test strategyKarim Arabi, Bozena Kaminska, Stephen K. Sunter. 40-45 [doi]
• A Design For Test Perspective on I/O ManagementKamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer. 46 [doi]
• Opportunities and pitfalls in HDL-based system designRajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi. 56 [doi]
• Issues on the architecture and the design of distributed shared memory systemsNian-Feng Tzeng, Steven Wallach. 60-61 [doi]
• Design issues for distributed shared-memory systemsDaniel Lenoski. 62-62 [doi]
• The Tempest approach to distributed shared memoryDavid A. Wood, Mark D. Hill, James R. Larus. 63 [doi]
• Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow GraphsPradeep Prabhakaran, Prithviraj Banerjee. 66-71 [doi]
• Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource ConstraintsMark C. Johnson, Kaushik Roy. 72-77 [doi]
• Multiplexor Network Generation in High Level SynthesisYung-Ming Fang, D. F. Wong. 78 [doi]
• Multimodal query support in database serversWilliam O Connell, Grace Au, David Schrader. 86-92 [doi]
• Evaluation of high speed LAN protocols as multimedia carriers W. Melody Moh, Yu-Feng Chung, Teng-Sheng Moh, Joanna Wang. 93 [doi]
• A Compact Neural Network Based CDMA Receiver for Multimedia Wireless CommunicationDavid C. Chen, Bing J. Sheu, Theodore W. Berger. 99 [doi]
• Space Cutting Approaches for Repairing MemoriesYinan N. Shen, Nohpill Park, Fabrizio Lombardi. 106-111 [doi]
• Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICsAlex Orailoglu. 112-117 [doi]
• Pausible Clocking: A First Step Toward Heterogeneous SystemsKenneth Y. Yun, Ryan P. Donohue. 118 [doi]
• On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL DescriptionsPeter Walker, Sumit Ghosh. 128-130 [doi]
• Arithmetic Pattern Generators for Built-In Self-TestAlbrecht P. Stroele. 131-134 [doi]
• Testing of embedded A/D converters in mixed-signal circuitNaim Ben Hamida, Bechir Ayari, Bozena Kaminska. 135-136 [doi]
• A VLSI array architecture with dynamic frequency clockingN. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar. 137-140 [doi]
• An integrated microspacecraft avionics architecture using 3D multichip module building blocksLeon Alkalai, Wai-Chi Fang. 141-144 [doi]
• New Challenges for Video Servers: Performance of Non-Linear Applications under User ChoiceMichael Kozuch, Wayne Wolf, Andrew Wolfe. 145-146 [doi]
• An output-shared buffer ATM switchJin Li. 147-148 [doi]
• A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer ManagementChie Dou, Ming-Der Shieh. 149 [doi]
• Future Challenges of Deep Sub-Micron Processer DesignMark Dermott. 154 [doi]
• Fault Location based on Circuit PartitioningIrith Pomeranz, Sudhakar M. Reddy. 154 [doi]
• Design and Implementation of a new Synchronization Method for High-Speed Cell-based Network InterfacesAlex Maniatopoulos, Theodore Antonakopoulos, Vassilios Makios. 158-164 [doi]
• Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection NetworkJosé Cruz-Rivera, D. Scott Wills, Thomas K. Gaylord, Elias N. Glytsis. 165-169 [doi]
• MMPacking: A Load and Storage Balancing Algorithm for Distributed Multimedia ServersDimitrios N. Serpanos, Leonidas Georgiadis, T. Bouloutas. 170 [doi]
• Memory Hierarchy Synthesis of a Multimedia Embedded ProcessorSteve Fu. 176-184 [doi]
• High Speed Video Board as a Case Study for Hardware-Software Co-DesignDirk Herrmann. 185-190 [doi]
• VLIW-Processors under Periodic Real Time ConstraintsJean-Paul Theis, Lothar Thiele. 191 [doi]
• Embedded Systems Design with Frontend CompilersC. Alba, Luigi Carro, A. Lima, Altamiro Amadeu Susin. 200 [doi]
• Microarchitecture Support for Reducing Branch Penalty in a Supercscaler ProcessorMamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu. 208-216 [doi]
• Profile-Driven Generation of Trace SamplesPradeep K. Dubey, Ravi Nair. 217-224 [doi]
• Branch-Directed and Stride-Based Data Cache PrefetchingYue Liu, David R. Kaeli. 225-230 [doi]
• Global Bus Design of a Bus-Based COMA Multiprocessor DICEGyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney. 231 [doi]
• Fault Location Based on Circuit PartitioningIrith Pomeranz, Sudhakar M. Reddy. 242-247 [doi]
• A Better ATPG Algorithm and Its Design PrinciplesLi-C. Wang, M. Ray Mercer, Thomas W. Williams. 248-253 [doi]
• Using Functional Information and Strategy Switching in Sequential ATPGJaehong Park, M. Ray Mercer. 254-260 [doi]
• Modeling the Difficulty of Sequential Automatic Test Pattern GenerationThomas E. Marchok, Wojciech Maly. 261 [doi]
• Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging TechnologSteven P. Larcombe, David J. Prendergast, Neil A. Thacker, Peter A. Ivey. 274-279 [doi]
• Module Generators for a Regular Analog LayoutJ. Kampe, C. Wisser, G. Scarbata. 280-292 [doi]
• A Scalable Resistor-less PLL Design for PowerPCTM MicroprocessorsJose Alvarez, Hector Sanchez, Roger Countryman, Mike Alexander, Carmine Nicoletta, Gianfranco Gerosa. 293-300 [doi]
• Design Tradeoffs and Experience with Motorola PowerPC? Migration ToolMauricio Breternitz Jr., A. Manikonda, M. Ommerman, W. Su, A. Thornto. 301 [doi]
• Embedded System Design Issues (The Rest of the Story)Philip Koopman. 310 [doi]
• A Scaling Scheme and Optimization Methodology for Deep Sub-Micron InterconnectSoo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, J. Moll. 320-325 [doi]
• Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAsFran Hancheck, Shantanu Dutt. 326-331 [doi]
• Clock-Delayed Domino for Adder and Combinational Logic DesigGin Yee, Carl Sechen. 332 [doi]
• DNA computations can have global memoryRichard J. Lipton. 344 [doi]
• A formal verification technique for embedded softwareOlivier Thiry, Luc J. M. Claesen. 352-357 [doi]
• Binary decision diagrams on network of workstationRajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 358-364 [doi]
• Distributed Binary Decision Diagrams for Verification of Large CircuitPrakash Arunachalam, Craig M. Chase, Dinos Moundanos. 365-370 [doi]
• The use of random simulation in formal verificationFlorian Krohm, Andreas Kuehlmann, Arjen Mets. 371 [doi]
• Large Standard Cell Libraries and Their Impact on Layout Area and Circuit PerformancBingzhong Guan, Carl Sechen. 378-383 [doi]
• Implicit Test Sequences Compaction for Decreasing Test Application CosRoberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi. 384-382 [doi]
• Dichotomy-based Model for FSM Power MinimizationLakshmikant Bhupathi, Liang-Fang Chao. 390-395 [doi]
• Optimal single probe traversal algorithm for testing of MCM substratRajesh Pendurkar, Abhijit Chatterjee, Craig A. Tovey. 396 [doi]
• RSFQ: What We Know and What We Don tStas Polonsky. 406-412 [doi]
• Efficient Delay-Insensitive RSFQ CircuitsPriyadarsan Patra, Donald S. Fussell. 413-418 [doi]
• Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum DevicesYoshio Kameda. 419-425 [doi]
• Exact Dichotomy-based Constrained EncodiOlivier Coudert, C.-J. Richard Shi. 426-431 [doi]
• Latch Redundancy Removal Without Global ResetShaz Qadeer, Robert K. Brayton, Vigyan Singhal. 432-439 [doi]
• A Practical Algorithm for Retiming Level-Clocked CircuitsNaresh Maheshwari, Sachin S. Sapatnekar. 440 [doi]
• Distributed EDA Tool Integration: The PPP ParadigmLuca Benini, Alessandro Bogliolo, Giovanni De Micheli. 448-453 [doi]
• A Method for Analog Circuits VisualizationBogdan G. Arsintescu. 454-459 [doi]
• Cycle-Based Timing Simulations Using Event-StreamKei-Yong Khoo, Alan N. Willson Jr.. 460 [doi]
• Reducing State Loss For Effective Trace Sampling of Superscalar ProcessorsThomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes. 468-477 [doi]
• Can Trace-Driven Simulators Accurately Predict Superscalar Performance?Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen. 478-485 [doi]
• The Augmint multiprocessor simulation toolkit for Intel x86 architecturesAnthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas. 486-490 [doi]
• Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliersJanardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang. 492-499 [doi]
• A VLSI chip for image compression using variable block size segmentationS. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri. 500-505 [doi]
• On Design of Efficient Square GeneratorChin-Long Wey. 506
• Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapathH. Fatih Ugurdag, Thomas E. Fuhrman. 514-529 [doi]
• Synthesis of Multi-Dimensional Applications in VHDLNelson L. Passos, Edwin Hsing-Mean Sha. 530 [doi]
• A New Non-Restoring Square Root Algorithm and its VLSI ImplementationYamin Li, Wanming Chu. 538-544 [doi]
• Early Zero DetectionDavid R. Lutz, D. N. Jayasimha. 545 [doi]
• FPGA Module MinimizationD. Kuguris, Spyros Tragoudas. 566-571 [doi]
• An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA DesigJason Cong, Chang Wu. 572-578 [doi]
• Multiway Partitioner for High Performance FPGA Based Board ArchitectureVijayanand Sankarasubramanian, Dinesh Bhatia. 579 [doi]