Yun-Nan Chang - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 31 from 31

2023

Design of Low-cost IOU Circuit for Post-processing of Object DetectionYun-Nan Chang. gcce 2023: 407-408 [doi]

2019

Scaling Bit-Flexible Neural NetworksYun-Nan Chang, Yu-Tang Tin. isocc 2019: 253-254 [doi]

Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early TerminationYun-Nan Chang, Guan-Jhen Chen. elinfocom 2019: 1-3 [doi]

2017

A fast ray tracing scheme for dynamic scenesYun-Nan Chang, Chin-Lun Yang. codit 2017: 872-875 [doi]

2016

Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generatorYun-Nan Chang. newcas 2016: 1-4 [doi]

2015

2014

Design of a 2D graphics front-end rendering processorYun-Nan Chang, Ting-Chi Tong. asap 2014: 70-71 [doi]

2013

Two-level hierarchical fill-buffer for graphics rendering systemsYun-Nan Chang. newcas 2013: 1-4 [doi]

Architectures for digital filters using stochastic computingYun-Nan Chang, Keshab K. Parhi. icassp 2013: 2697-2701 [doi]

Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line BufferTing-Chi Tong, Yun-Nan Chang. tvlsi, 21(7):1246-1259, 2013. [doi]

2010

A Multibank Memory-Based VLSI Architecture of DVB Symbol DeinterleaverYun-Nan Chang. tvlsi, 18(5):840-843, 2010. [doi]

Digit-Serial Pipeline Sorter ArchitectureYun-Nan Chang. vlsisp, 61(2):241-249, 2010. [doi]

2009

2008

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT DesignYun-Nan Chang. tcas, 55-II(12):1234-1238, 2008. [doi]

An Efficient Design of H.264 Inter Interpolator with Bandwidth OptimizationYun-Nan Chang, Ting-Chi Tong. vlsisp, 53(3):435-448, 2008. [doi]

A low-cost dual-mode deinterleaver designYun-Nan Chang. tce, 54(2):326-332, 2008. [doi]

2005

Design of an efficient memory-based DVB-T channel decoderYun-Nan Chang. iscas 2005: 5019-5022 [doi]

2003

Design of soft-output Viterbi decoders with hybrid trace-back processingYun-Nan Chang. iscas 2003: 69-72 [doi]

An Efficient In-Place VLSI Architecture for Viterbi AlgorithmYun-Nan Chang. vlsisp, 33(3):317-324, 2003. [doi]

An efficient pipelined FFT architectureYun-Nan Chang, Keshab K. Parhi. tcasII, 50(6):322-325, 2003. [doi]

2000

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoderYun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi. jssc, 35(6):826-834, 2000. [doi]

1999

Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systemsHiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi. icassp 1999: 1913-1916 [doi]

Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systemsHiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi. cicc 1999: 589-592 [doi]

1998

Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional UnitsYun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi. vlsisp, 19(3):243-256, 1998. [doi]

High-performance digit-serial complex-number multiplier-accumulatorYun-Nan Chang, Keshab K. Parhi. In ICCD. 1998: 211-213 [doi]

1997

Design and Implementation of Low-Power Digit-Serial MultipliersYun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi. iccd 1997: 186-195

1996

Loop-List Scheduling for Heterogeneous Functional UnitsYun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi. glvlsi 1996: 2-7 [doi]

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliersJanardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang. iccd 1996: 492-499 [doi]

Sign in or sign up to see more results.

runs on WebDSL