Table of Contents

• Simulation and modeling of intermodulation distortion in communication circuitsJess Chen, Dan Feng, Joel R. Phillips, Kenneth S. Kundert. 5-8 [doi]
• Intermodulation analysis of mixer circuits based on frequency domain relaxation methodAkio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Masayuki Takahashi, Kimihiro Ogawa. 9-12 [doi]
• Grid selection strategies for time-mapped harmonic balance simulation of circuits with rapid transitionsOgnen J. Nastov, Jacob K. White. 13-16 [doi]
• Automated macromodelling of "nonlinear" wireless blocksJaijeet Roychowdhury. 17-20 [doi]
• A frequency-domain, Volterra series-based behavioral simulation tool for RF systemsIason Vassiliou, Alberto L. Sangiovanni-Vincentelli. 21-24 [doi]
• A fully synthesizable parameterized Viterbi decoderR. Burger, G. Cesana, Maurizio Paolini, Maura Turolla, S. Vercelli. 27-30 [doi]
• Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioningMauro Chinosi, Roberto Zafalon, Carlo Guardiani. 31-34 [doi]
• Watermarking-based copyright protection of sequential functionsIlhami Tomnoglu, Edoardo Charbon. 35-38 [doi]
• Hierarchical watermarking for protection of DSP filter coresAzra Rashid, Jeet Asher, William H. Mangione-Smith, Miodrag Potkonjak. 39-42 [doi]
• Multi-project management in real timeKen W. K. Au, Trina M. Mann. 45-52 [doi]
• Integrated IC design approach based on software engineering paradigmSunsil Sinha, Mahesh Mehendale. 53-56 [doi]
• Beyond 1 GHzH. Peter Hofstee, Kevin J. Nowka. 57-61 [doi]
• A scalable architecture for MPEG-4 embedded zero tree codingBart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Marc Engels, Ivo Bolsens. 65-68 [doi]
• A MPEG4 programmable codec DSP with an embedded pre/post-processing engineShun-ichi Kurohmaru, Masatoshi Matsuo, Hiromasa Nakajima, Y. Kohashi, Tomonori Yonezawa, Toshihiro Mori-iwa, Masahiro Ohashi, M. Toujima, Tsuyoshi Nakamura, Mana Hamada, Takashi Hashimoto, H. Fujimoto, Yasuo Iizuka, Junji Michiyama, H. Komori. 69-72 [doi]
• A low-power single-chip MPEG-2 CODEC LSIYukitoshi Tsuboi, Hideo Arai, Masaru Takahashi, Masuo Oku. 73-76 [doi]
• Embedding DRAM in single chip MPEG1 codec LSIT. Fujihira, H. Ohtsubo, H. Sakurai, K. Ohi. 77-80 [doi]
• The changing landscape of system-on-a-chip designAnn Marie Rincon, William R. Lee, Michael Slattery. 83-90 [doi]
• Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV applicationG. Bollano, S. Claretto, L. Licciardi, A. Montanaro, L. Pilati, Maura Turolla. 91-94 [doi]
• A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation coresSatoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida. 95-98 [doi]
• An analog record, playback and processing system on a chip for mobile communications devicesGeoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter Holzmann, Oliver C. Kao, Carl R. Palmer, Aditya Raina. 99-102 [doi]
• Single GSM mixed signal superchip with 96k bytes FLASH and low power micro-controllerKang Lee, Benjamin Ng, Andrew Wang, Ray Kuhn, Derrick Johnson, Ross Kohler. 103-106 [doi]
• CMOS pipelined ADC employing dither to improve linearityH. Scott Fetterman, David G. Martin, David A. Rich. 109-112 [doi]
• A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADCIuri Mehr, Larry Singer. 113-116 [doi]
• An 8-bit 150-MHz CMOS A/D converterYun-Ti Wang, Behzad Razavi. 117-120 [doi]
• A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINADEric Fogleman, Ian Galton, William Huff, Henrik Jensen 0001. 121-124 [doi]
• A spurious-free delta-sigma DAC using rotated data weighted averagingRussell E. Radke, Aria Eshraghi, Terri S. Fiez. 125-128 [doi]
• A bandpass sigma-delta modulator IC with digital branch-mismatch correctionVittorio Comino, Allen C. Lu. 129-132 [doi]
• A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applicationsAngelo Nagari, Alessandro Mecchia, Ermes Viani, Sergio Pernici, Pierangelo Confalonieri, Germano Nicollini. 133-136 [doi]
• A low-triggering circuitry for dual-direction ESD protectionAlbert Z. Wang, Chen-Hui Tsay. 139-142 [doi]
• New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC'sMing-Dou Ker, Wen-Yu Lo, Chung-Yu Wu. 143-146 [doi]
• Test chips for die stress characterization using arrays of CMOS sensorsArthur T. Bradley, Richard C. Jaeger, Jeffrey C. Suhling, Y. Zou. 147-150 [doi]
• Digital detection of parametric faults in data convertersBapiraju Vinnakota, Ramesh Harjani. 151-154 [doi]
• Testing analog circuits by supply voltage variation and supply current monitoringYavuz Kiliç, Mark Zwolinski. 155-158 [doi]
• TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generationYiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah. 159-162 [doi]
• Simplifying in-system programming: evolving standards for ISPBryon Moyer. 165-170 [doi]
• Circuit design, transistor sizing and wire layout of FPGA interconnectYaughn Betz, Jonathain Rose. 171-174 [doi]
• A next generation architecture optimized for high density system level integrationRichard Cliff, Srinivas Reddy, Cameron McClintock, David Jefferslon, Christopher Lane, Ketan Zaveri, Manuel Mejia, Andy Lee, Ninh Ngo, Risa Altaf, Bruce Pedersen, Frank Heile, Jay Schleicher, John Turner. 175-178 [doi]
• A fast, predictable FPGA with PLLs, dual port SRAMs and active repeatersPaul T. Sasaki, Yogendra Bobra, Warren E. Cory, Atul V. Cihia, Suresh M, Menon, Madhavi Kola, Mammen Thomas, Prasad Rau, Arch Zaliznyak. 179-182 [doi]
• A field programmable system chip which combines FPGA and ASIC circuitryWilliam B. Andrew, Glenn Carl, Ravi K. Charath, James F. Hoff, Ron Modo, Hung Nguyen, William Smith, David Rhein, Joe Schulingkamp, Carolyn W. Spivak, James P. Steward, Akila Subramaniam. 183-186 [doi]
• A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programmingBrad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello. 187-190 [doi]
• Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAsSimon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung. 191-194 [doi]
• RF transmitter architectures and circuitsBehzad Razavi. 197-204 [doi]
• A 4-dB NF GPS receiver front-end with AGC and 2-b A/DMark Cloutier, Theodore Varelas, Christian Cojocaru, Florinel Balteanu. 205-208 [doi]
• Mixed-signal quadrature demodulator with a multi-carrier regeneration systemJoop P. M. Van Lammeren, Roy W. B. Wissing. 209-212 [doi]
• An ultralow power single-chip CMOS 900 MHz receiver for wireless pagingHooman Darabi, Asad A. Abidi. 213-216 [doi]
• A 5.2 GHz 3.3 V I/Q SiGe RF transceiverJean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer. 217-220 [doi]
• A Si/SiGe HBT timing generator IC for high-bandwidth impulse radio applicationsDavid Rowe, Bret Pollack, James Pulver, W. Chon, Preston Jett, Larry W. Fullerton, Lawrence Larson. 221-224 [doi]
• Converting an SRAM from bulk Si to partially depleted SOIMichael Wood, George Smith, John Pennings. 227-230 [doi]
• Multiple twisted data line techniques for coupling noise reduction in embedded DRAMsDong-Sun Min, Dietrich W. Langer. 231-234 [doi]
• A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reloadSteven Sullivan, Brad R. Johnson, Douglas Reid, Scott A. Taylor. 235-238 [doi]
• A self-timed, fully-parallel content addressable queue for switching applicationsJason Podaima, Glenn Gulak. 239-242 [doi]
• A 1.4 V 60 MHz access, 0.25 μm embedded flash EEPROMTomonori Kataoka, Ikuo Fuchigami, Yoichi Nishida, Tomoo Kimura, Rie Aruga, Yasushi, Junji Michiyama. 243-246 [doi]
• Analog sense amplifiers for high density NOR flash memoriesMarco Pasotti, Pier Luigi Rolandi, Roberto Canegallo, Danilo Gerna, Giovanni Guaitini, Frank Lhermet, Alan Kramer. 247-250 [doi]
• A CMOS mixed-signal 100 Mb/s receive architecture for fast EthernetAyal Shoval, Omid Shoaei, Kathleen O. Lee, Robert H. Leonowich. 253-256 [doi]
• A dual-speed 125 Mbaud/10 Mbaud CMOS transmitter for Fast EthernetOmit Shoaei, Ayal Shoval, Robert H. Leonowich. 257-260 [doi]
• Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 μm CMOSKamran Iravani, Farid Saleh, D. Lee, Patrick Fung, Paul Ta, Gary Miller. 261-264 [doi]
• A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communicationsLizhong Sun, Tad A. Kwasniewski. 265-268 [doi]
• A 3 V-CMOS low distortion class AB line driver suitable for HDSL applicationsMichael S. Kappes. 269-272 [doi]
• A 2.5-Gb/s one-chip receiver module for gigabit-to-the-home (GTTH) systemMasaaki Soda, S. Shiori, Takenori Morikawa, M. Tachigori, I. Watanabe, Makoto Shibutani. 273-276 [doi]
• Design considerations for distributed microsensor systemsAnantha P. Chandrakasan, Raj Amirtharajah, Seong-Hwan Cho, James Goodman 0001, Gangadhar Konduri, Joanna Kulik, W. Rabiner, Alice Wang. 279-286 [doi]
• A single chip CMOS APS camera with direct frame difference outputShyh-Yih Ma, Liang-Gee Chen. 287-290 [doi]
• Band runlength coding for low-power continuous micro-monitorsMinoru Fujishima, Yuji Kiniwa, Koichiro Hoh. 291-294 [doi]
• A data-driven micropipeline structure using DSDCVSLSanu hlathew, Ramalingam Sridhar. 295-298 [doi]
• A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cellsYongsam Moon, Jongsang Choi, Kyeongho Lee, Deog Kyoon Jeong, Min-Kyu Kim. 299-302 [doi]
• A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessorHee-Tae Ahn. 303-305 [doi]
• Hard disk drive read channels: technology and trendsHemat Thapar, Sang-Soo Lee, Cormac Conroy, Richard Contreras, Alfred Yeung, Jenn-Gang Chern, Tzuwang Pan, Shih-Ming Shih. 309-316 [doi]
• A 450 Mbit/s EPR4 PRML read/write channelMarco Demicheli, Giacomino Bollati, Paolo Gadducci, L. Affortunati, R. Alini, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, Stefano Marchese, D. Ottini, Valerio Pisati, S. Portaluri, A. Rossi, P. Savo, C. Tonci, R. Castello. 317-320 [doi]
• A CMOS two-path tree search detectorXiaodong Wang, Richard R. Spencer. 321-324 [doi]
• A 110 MHz 350 mW 0.6μ CMOS 16-state generalized-target Viterbi detector for disk drive read channelsSrinath Sridharan, L. Richard Carley. 325-328 [doi]
• A BiCMOS preamplifier/write-driver IC for tape driveMichael P. Flynn, Michael Twohig, Raymond Byrne, Hooman Reyhani, John Ryan. 329-332 [doi]
• A BiCMOS 1× to 5× combined analog frontend IC for DVD-ROM and movie playersStefano Marchese, Valerio Pisati, S. Portaluri, A. Savo, G. Vai, Steffen Lehr, Volker Neiss, C. Buechler, F. Zucker. 333-337 [doi]
• Device and circuit design issues in SOI technologyGhavam G. Shahidi, Atul Ajmera, Fariborz Assaderaghi, Ronald J. Bolam, Harold Hovel, Effendi Leobandung, Werner Rausch, Devendra Sadana, Dominic Schepis, Lawrence F. Wagner, Larry Wissel, Kun Wu, Bijan Davai. 339-346 [doi]
• The first copper ASICs: A 12M-gate technologyJeannie H. Panner, Thomas R. Bednar, Patrick H. Buffet, Douglas W. Kemerer, Douglas W. Stout, Paul S. Zuchowski. 347-350 [doi]
• Wireless communication integrated circuits with CMOS-compatible SiGe HBT technology modulesWolfgang Winkler, Johannes Borngräber, Heide Erzgraeber, Ha. Erzgraber, Bernd Heinemann, Dieter Knoll, H. Jörg Osten, Michael Pierschel, Klaus Pressel, Peter Schley. 351-358 [doi]
• Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent designMikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo. 359-363 [doi]
• Substrate-induced high-frequency noise in deep sub-micron MOSFETs for RF applicationsS. V. Kishore, Glenn Chang, Georgios Asmanis, Chris Hull, Frederic Stubbe. 365-368 [doi]
• RF simulations and physics of the channel noise parameters within MOS transistorsTajinder Manku, Michael S. Obrecht, Yi Lin. 369-372 [doi]
• Oscillator phase noise: a tutorialThomas H. Lee. 373-380 [doi]
• Noise analysis of a VCO with automatic amplitude controlMihai A. Margarit, Joo Leong Tham, M. Jamal Deen, Robert G. Meyer. 381-384 [doi]
• Modeling and simulation of noise in analog/mixed-signal communication systemsAlper Demir 0001, Jaijeet Roychowdhury. 385-393 [doi]
• IP reuse creation for system-on-a-chip designPierre J. Bricaud. 395-401 [doi]
• w/L: An interface description language for IP reuseKei Suzuki, Kouji Ara, Kazuo Yano. 403-406 [doi]
• A new method for reuse-driven design of digital circuitsOlaf Heuser, Horst-Lothar Fiedler. 407-410 [doi]
• An integrated environment for configurable designsDavid Dignam, Ben Garlick, Ed Hutchins, Oren Rubinstein. 411-414 [doi]
• IP repository, a Web based IP reuse infrastructurePeter Schindler, Klara Weidenbacher, Thomas Zimmermann. 415-418 [doi]
• The challenge of designing global signals in UDSM CMOSSandy Taylor. 429-435 [doi]
• Clock verification in the presence of IR-drop in the power distribution networkSyed Zakir Hussain, Steften Rochel, David Overhauser, Resve Saleh. 437-440 [doi]
• Characterization and modeling of clock skew with process variationsPayman Zarkesh-Ha, Tony Mule, James D. Meindl. 441-444 [doi]
• Including inductive effects in interconnect timing analysisByron Krauter, Sharad Mehrotra, V. Chandramouli. 445-452 [doi]
• Return-limited inductances: a practical approach to on-chip inductance extractionKenneth L. Shepard, Zhong Tian. 453-456 [doi]
• An efficient inductance modeling for on-chip interconnectsLei He 0001, Norman Chang, Shen Lin, O. Sam Nakagawa. 457-460 [doi]
• Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extractionArani Sinha, Salim Chowdhury. 461-465 [doi]
• Power supply noise in future IC's: a crystal ball readingPatrik Larsson. 467-474 [doi]
• th CMOS integrated circuitsAkio Koyama, Masatoshi Tsuge, Jun'ya Kudo, Tatsuhiro Aida, Makio Uchida. 475-478 [doi]
• Substrate cross talk noise characterization and prevention in 0.35 mμm CMOS technologyJohn P. Z. Lee, Frank Wang, Abhijit Phanse, Linda C. Smith. 479-482 [doi]
• Substrate injection and crosstalk in CMOS circuitsJ. Briaire, K. S. Krisch. 483-486 [doi]
• A methodology for measurement and characterization of substrate noise in high frequency circuitsRanjit Gharpurey. 487-490 [doi]
• A review of substrate coupling issues and modeling strategiesRaminderpal Singh. 491-499 [doi]
• A wideband tunable CMOS channel-select filter for a low-IF wireless receiverFarbod Behbahani, Weeguan Tan, Ali Karimi-Sanjaani, Andreas Roithmeier, Asad A. Abidi. 501-504 [doi]
• th-order Bessel filter dedicated to digital standard processesDominique Python, Alain-Serge Porret, Christian C. Enz. 505-508 [doi]
• pp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPFTetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai. 509-512 [doi]
• A 2.125 Gbaud 1.6 kΩ transimpedance preamplifier in 0.5 μm CMOSSunderarajan S. Mohan, Thomas H. Lee. 513-516 [doi]
• A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency dividerHamid R. Rategh, Hirad Samavati, Thomas H. Lee. 517-520 [doi]
• A 3.25 Gb/s injection locked CMOS clock recovery cellThaddeus Gabara. 521-524 [doi]
• A novel high precision adjustment method for the transconductance of a MOSFETMika Tiilikainen. 525-529 [doi]
• A new generation of DSP architecturesBryan Ackland, Paul D'Arcy. 531-536 [doi]
• A single-chip 1.6 billion 16-b MAC/s multiprocessor DSPBryan D. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, Asawaree Kalavade, J. Knobloch, E. Micca, M. Moturi, Chris J. Nicol, Jay H. O'Neill, Joe Othmer, Eduard Sackinger, Kanwar Jit Singh, J. Sweet, C. J. Terman, Joseph Williams. 537-540 [doi]
• A DSP Reed-Solomon coderTod Wolf. 541-544 [doi]
• Versatile beamforming ASIC architecture for broadband fixed wireless accessJi-Ning Duan, Li-Jen Ko, Babak Daneshrad. 545-548 [doi]
• A single-chip narrowband frequency domain excisor for a Global Positioning System (GPS) receiverPaul T. Capozza, Brian J. Holland, Thomas M. Hopkinson, Roberto L. Landrau. 549-552 [doi]
• 470 MHz digital filter on delta-sigma modulated signalsSilas Li, David Lewis. 553-556 [doi]
• Wave pipelining YADDs-a feasibility studyArindam Mukherjee, Malgorzata Marek-Sadowska, Stephen I. Long. 559-562 [doi]
• Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIsKouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai. 563-566 [doi]
• ANACONDA: robust synthesis of analog circuits via stochastic pattern searchRodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums. 567-570 [doi]
• Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boardsYhonkyong Choi, Chong S. Rim. 571-574 [doi]
• Measurements and analyses of substrate noise waveform in mixed signal IC environmentMakoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata. 575-578 [doi]
• An extended bipolar transistor model for substrate crosstalk analysisM. Klemme, Erich Barke. 579-582 [doi]
• Substrate network modeling for CMOS RF circuit simulationSuet Fong Tin, Kartikeya Mayaram. 583-586 [doi]
• Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systemsHiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi. 589-592 [doi]
• A low-power direct digital frequency synthesizer architecture for wireless communicationsAbdellatif Bellaouar, Michael S. Obrecht, Amr M. Fahim, Mohamed I. Elmasry. 593-596 [doi]
• A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applicationsW. H. Chang, D. R. Pehlke, R. Yu. 597-600 [doi]
• Giga bit per second per pin differential CMOS circuits for pseudo ECL signalingHormoz Djahanshahi, Flemming Hansen, C. André T. Salama. 601-604 [doi]
• A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolutionPoki Chen, Shen-Iuan Liu. 605-608 [doi]
• Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controllerRegan Zane, Dragan Maksimovic. 609-612 [doi]
• A 1.5 GHz, sub-2 mW CMOS dual-modulus prescalerAbdelaziz Benachour, Sherif H. K. Embabi, Akbar Ali. 613-616 [doi]
• VSIA technical challengesHoward Sachs, Mark Birnbaum. 619-622 [doi]
• An efficient bus architecture for system-on-chip designBill Cordan. 623-626 [doi]
• A bus architecture centric configurable processor systemSteven Winegarden. 627-630 [doi]
• Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing systemPeter M. Nyasulu, Ralph Mason, W. Martin Snelgrove, Duncan G. Elliott. 631-634 [doi]
• The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuseJacobo Riesco, Juan Carlos Diaz, Pierre Plaza. 635-638 [doi]
• Design of high-Q varactors for low-power wireless applications using a standard CMOS processAlain-Serge Porret, Thierry Melly, Christian C. Enz. 641-644 [doi]
• A 1.3 GHz CMOS VCO with 28% frequency tuningFrancesco Svelto, Stefano Deantoni, Rinaldo Castello. 645-648 [doi]
• A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applicationsDirk Pfaff, Qiuting Huang. 649-652 [doi]
• Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architecturesAmr N. Hafez, Mohamed I. Elmasry. 653-656 [doi]
• A wideband quadrature LO generator in digital CMOSJeffrey Harrison, Neil Weste. 657-659 [doi]
• A 900-MHz, 0.8-μm CMOS low noise amplifier with 1.2-dB noise figureBrian A. Floyd, Jesal Mehta, Carlos Gamero, Kenneth K. O. 661-664 [doi]
• A 1 V 900 MHz image-reject downconverter in 0.5 μm CMOSJohn R. Long, Michael C. Maliepaard. 665-668 [doi]