Shen Lin - researchr alias

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Viewing Publication 1 - 33 from 33

2024

Technological topic analysis of standard-essential patents based on the improved Latent Dirichlet Allocation (LDA) modelChen Tian, Junyan Zhang, Dayong Liu, Qing Wang, Shen Lin. taasm, 36(9):2084-2099, September 2024. [doi]

2023

ERM-KTP: Knowledge-Level Machine Unlearning via Knowledge TransferShen Lin, Xiaoyu Zhang, Chenyang Chen, Xiaofeng Chen, Willy Susilo. cvpr 2023: 20147-20155 [doi]

CCA-Secure Identity-Based Matchmaking Encryption from Standard AssumptionsShen Lin, Yu Li, Jie Chen 0021. cisc 2024: 253-273 [doi]

2022

2015

A single-pattern matching algorithm base on twice jumps in the intrusion detection systemsZhongming Yang, Shen Lin. fskd 2015: 2593-2597 [doi]

2009

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC designDaisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata. cicc 2009: 219-222 [doi]

Early analysis for power distribution networksKai Wang, Aveek Sarkar, Norman Chang, Shen Lin. ispd 2009: 3-4 [doi]

2008

An Alternative Choice of Scratch-Pad Memory for Energy Optimization in Embedded SystemLing Ming, Zhang Yu, Shen Lin. icnsc 2008: 1641-1647 [doi]

2007

A methodology for analysis and verification of power gated circuits with correlated resultsAveek Sarkar, Shen Lin, Kai Wang. islped 2007: 351-354 [doi]

2004

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurementShen Lin, Makoto Nagata, Kenji Shimazake, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang. cicc 2004: 509-512 [doi]

2002

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertionYu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu. tvlsi, 10(6):799-805, 2002. [doi]

2001

2000

1999

An efficient inductance modeling for on-chip interconnectsLei He 0001, Norman Chang, Shen Lin, O. Sam Nakagawa. cicc 1999: 457-460 [doi]

1995

Techniques for fast circuit simulation applied to power estimation of CMOS circuitsPremal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh. islped 1995: 135-138 [doi]

1994

Process-variation-tolerant clock skew minimizationShen Lin, C. K. Wong. iccad 1994: 284-288 [doi]

1993

Circuit simulation for large interconnected IC networksShen Lin, Ernest S. Kuh. vlsi 1994: 333-342

Stepwise equivalent conductance circuit simulation techniqueShen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska. tcad, 12(5):672-683, 1993. [doi]

1992

A New Accurate and Efficient Timing SimulatorShen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska. vlsid 1992: 281-286 [doi]

Transient simulation of lossy coupled transmission linesShen Lin, Ernest S. Kuh. eurodac 1992: 126-131 [doi]

Transient Simulation of Lossy InterconnectShen Lin, Ernest S. Kuh. dac 1992: 81-86 [doi]

1991

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuitsShen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh. eurodac 1991: 142-148 [doi]

A fast and efficient algorithm for determining fanout trees in large networksShen Lin, Malgorzata Marek-Sadowska. eurodac 1991: 539-544 [doi]

1990

Delay and Area Optimization in Standard-Cell DesignShen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh. dac 1990: 349-352 [doi]

1989

Timing driven placementMalgorzata Marek-Sadowska, Shen Lin. iccad 1989: 94-97 [doi]

1970

An efficient heuristic procedure for partitioning graphsBrian W. Kernighan, Shen Lin. bstj, 49(2):291-307, 1970. [doi]

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