Abstract is missing.
- The single chip system eraJoseph Borel, J. Monnier, G. Matheron. 3-12
- Post-placement technology mappingDaniel R. Brasen, Arnold Ginetti. 15-24
- Optimal layout recycling based on graph theoretic linear programming approachYuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe. 25-34
- A family of module generators for the layout synthesis of I/O buffersKim-Minh Nguyen, Martin C. Lefebvre. 35-44
- A 45° compaction algorithm handling overconstraintsLorenz Ladage, Georg Lodde. 45-54
- Personal Communicators: A better way to stay in touchHermann Hauser. 57-61
- Design of a GaAs redundant dividerImed Moussa, Ali Skaf, Alain Guyot. 63-72
- An ASIC array architecture for the DITPOS algorithmPoul Martin Rands Jensen. 73-82
- Performance of object caching for object-oriented systemsJ. Morris Chang, Edward F. Gehringer. 83-91
- A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functionsAli Skaf, Jean-Claude Bajard, Alain Guyot, Jean-Michel Muller. 93-100
- Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan designMichael Gössel, Egor S. Sogomonyan. 103-111
- Partitioning and hierarchical description of self-testable designsAlbrecht P. Stroele. 113-122
- Test of single fault tolerant controllers in VLSI circuitsRégis Leveugle. 123-132
- A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logicW. A. J. Waller, S. M. Aziz. 133-142
- Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensorsD. Poussart. 145-150
- Single board image processing unit for vehicle guidanceJ. Schönfeld, Peter Pirsch. 151-160
- Implementation of the volume rendering algorithm using a low-power design-styleJaap Smit, Mark J. Bentum, Martin M. Samsom. 161-168
- Design of a dedicated neural network on silicon: application to optical character recognitionD. Jacquet, Gabriele Saucier. 169-178
- ARM6: Processor design for high performance at low powerMike Muller. 181-189
- A new method for retiming multi-functional processing unitsAlbert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens. 191-200
- A transformational approach to asynchronous high-level synthesisGanesh Gopalakrishnan, Venkatesh Akella. 201-210
- A micropipelined ARMStephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods. 211-220
- A high performance RISC microprocessorF. Poirier, Jean-Claude Heudin, M. Belleville, C. Jaffard. 221-228
- Probabilistic power consumption estimation in digital circuitsWolfgang Röthig, Elmar U. K. Melcher, Michel Dana. 231-240
- Solving the partial differential equations of transmission lines with wave digital filtersMaximilian Erbar, Ingo Könenkamp, Ernst-Helmut Horneber. 241-250
- Parallel harmonic balanceM. Schneider, Utz Wever, Qinghua Zheng. 251-260
- Estimating lower hardware bounds in high-level synthesisNorbert Wehn, Manfred Glesner, C. Vielhauer. 261-270
- Ultra high speed CMOS designChrister Svensson, Jiren Yuan. 273-282
- The implementation of a MCM associative string processorClaus M. Habiger, Ian P. Jalowiecki. 283-289
- Superconductive interconnections in multi-chip modulesBertrand Cabon, T. V. Dinh, J. Chilo. 291-298
- A multilayer channel router based on optimal multilayer net assignmentMikiko Sode Tanaka, Masaki Ishikawa. 301-310
- The chaos router chip: design and implementation of an adaptive routerKevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille. 311-320
- A new performance-driven global routing algorithm for gate arrayTianxiong Xue, Takashi Fujii, Ernest S. Kuh. 321-330
- Circuit simulation for large interconnected IC networksShen Lin, Ernest S. Kuh. 333-342
- Bondgraph execution as a new algorithm for circuit simulationM. Müller. 343-352
- Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulatorAvinash C. Palaniswamy, Philip A. Wilsey. 353-362