Gabriele Saucier - researchr alias

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Viewing Publication 1 - 80 from 80

2002

Who Owns the Platform?Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier. date 2002: 238-239 [doi]

E-Design Based on the Reuse ParadigmL. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier. date 2002: 214-220 [doi]

2000

FPGA Technology Snapshot: Current Devices and Design ToolsHelena Krupnova, Gabriele Saucier. rsp 2000: 200 [doi]

FPGA-Based Emulation: Industrial and Custom Prototyping SolutionsHelena Krupnova, Gabriele Saucier. fpl 2000: 68-77 [doi]

1999

1998

1997

A Hierarchy-Driven FPGA Partitioning MethodHelena Krupnova, Ali Abbara, Gabriele Saucier. dac 1997: 522-525 [doi]

Synthesis and Floorplanning for Large Hierarchical FPGAsHelena Krupnova, Christian Rabedaoro, Gabriele Saucier. fpga 1997: 105-111 [doi]

Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGABernard Laurent, G. Bosco, Gabriele Saucier. fpl 1997: 462-471

1995

Design of defect-tolerant scan chains for MCMs with an active substrateP. Brahic, Régis Leveugle, Gabriele Saucier. dft 1995: 252-260 [doi]

Efficient synthesis of fault-tolerant controllersR. Rochet, Régis Leveugle, Gabriele Saucier. date 1995: 593 [doi]

1994

FPGA Partitioning for Critical PathsDaniel R. Brasen, Gabriele Saucier. eurodac 1994: 99-103

Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural NetworkD. Jacquet, Gabriele Saucier. eurodac 1994: 256-260

Design Automation Tools for FPGA Design (Panel)Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier. dac 1994: 676 [doi]

Alternative Approaches to Fault Detection in FSMsRégis Leveugle, R. Rochet, Gabriele Saucier. dft 1994: 271-279

The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness AnalysisRégis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn. TC, 43(12):1398-1406, 1994.

Taking Advantage of ASICs to Improve Dependability with Very Low OverheadsT. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier. eurodac 1994: 14-18

Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing ModelingC. Safinia, Régis Leveugle, Gabriele Saucier. eurodac 1994: 349-353

1993

Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAsPierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier. tcad, 12(7):913-925, 1993. [doi]

Design of a dedicated neural network on silicon: application to optical character recognitionD. Jacquet, Gabriele Saucier. vlsi 1994: 169-178

Functional versus random test generation for sequential circuitsMargot Karam, Gabriele Saucier. et, 4(1):33-41, 1993. [doi]

Influence of Error Correlations on the Signature Analysis AliasingRégis Leveugle, X. Delord, Gabriele Saucier. iccd 1993: 584-587

A Synthesis Tool for Fault-Tolerant Finite State MachinesRégis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot. ftcs 1993: 502-511

Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC CodesR. Rochet, Régis Leveugle, Gabriele Saucier. dft 1993: 9-16

Partitioning with cone structuresGabriele Saucier, Daniel R. Brasen, J. P. Hiol. iccad 1993: 236-239 [doi]

Lexicographical expressions of Boolean functions with application to multilevel synthesisGabriele Saucier, Pierre Abouzeid. tcad, 12(11):1642-1654, 1993. [doi]

1992

Logic Synthesis for Automatic LayoutPierre Abouzeid, Régis Leveugle, Gabriele Saucier. ifip10-2 1993: 335-343

Specification and Synthesis of Communicating Finite State MachinesH. Belhadj, L. Gerbaux, Marie-Claude Bertrand, Gabriele Saucier. ifip10-2 1993: 91-102

Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision DiagramsT. Besson, H. Bouzouzou, M. Crastes, I. Floricica, Gabriele Saucier. iccd 1992: 163-167

Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit ProcessorsAhmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe. Computer, 25(4):29-39, 1992.

Automatic synthesis of large Moore sequencersLaurent Gerbaux, Gabriele Saucier. integration, 13(3):259-281, 1992. [doi]

Synthesis of large controllers using ROM or PLA generatorsL. Gerbaux, Régis Leveugle, Gabriele Saucier. ifip10-2 1993: 47-59

ASYL: A Control Driven RTL Synthesis System using Library BlocksAnne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier. ifip10-2 1993: 275-291

1991

A reconfigurable wafer-scale memoryAhmed Boubekeur, Gabriele Saucier, Jacques Trilhe. jssc, 26(10):1423-1432, October 1991. [doi]

A Technology Mapping Method Based On Perfect And Semi-Perfect MatchingsM. Crastes, K. Sakouti, Gabriele Saucier. dac 1991: 93-98 [doi]

Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC MultiprocessorsX. Delord, Gabriele Saucier. itc 1991: 936-945

State Assignment Based on the Reduced Dependency Theory and Recent Experimental ResultsChristopher Duff, Gabriele Saucier. iccad 1991: 222-225

Hierarchical Test Generation Based on Delayed PropagationMargot Karam, Régis Leveugle, Gabriele Saucier. itc 1991: 739-747

A New Approach to Control Flow Checking Without Program ModificationT. Michel, Régis Leveugle, Gabriele Saucier. ftcs 1991: 334-343

A Customizable Neural Processor for Distributed Neural NetworkJ. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, L. Masse-Navette. vlsi 1992: 167-176

1990

1989

1988

Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale SignalverarbeitungManfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe. gi 1988: 75-91

Optimized Layout of MOS CellsGhislaine Thuau, Gabriele Saucier. TC, 37(1):79-87, 1988.

1987

An Application of Exploratory Data Analysis Techniques to Floorplan DesignE. F. M. Kouka, Gabriele Saucier. dac 1987: 654-658 [doi]

ASYL: A Rule-Based System for Controller SynthesisGabriele Saucier, Michel Crastes de Paulet, Pascal Sicard. tcad, 6(6):1088-1097, 1987. [doi]

1986

A Rule-Based System for the Optimal State Assignment of ControllersE. Dupont, Jeanne Idt, Gabriele Saucier. fjcc 1986: 915-923

1985

Systematic and optimized layout of MOS cellsGabriele Saucier, Ghislaine Thuau. dac 1985: 53-61 [doi]

1984

1982

Top down design and testability of VLSI circuitsPhilippe Basset, Gabriele Saucier. dac 1982: 851-857 [doi]

Automatic generation of microprocessor test programsCatherine Bellon, A. Liothin, S. Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman. dac 1982: 566-573 [doi]

Protection Against External Errors in a Dedicated SystemCatherine Bellon, Gabriele Saucier. TC, 31(4):311-317, 1982.

1981

Hardware description levels and test for complex circuitsCatherine Bellon, Gabriele Saucier, J. M. Gobbi. dac 1981: 213-219 [doi]

1978

Dynamic Testing of Control UnitsChantal Robach, Gabriele Saucier. TC, 27(7):617-623, 1978.

1976

A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected ModulesM. Moalla, Gabriele Saucier, Joseph Sifakis, M. Zachariades. isca 1976: 20-27

Processor Testability and Design ConsequencesChantal Robach, Gabriele Saucier, J. Lebrun. TC, 25(6):645-652, 1976.

1975

On balancing hardware-firmware for designing a fault-tolerant computers' seriesBernard Courtois, Gabriele Saucier. micro 1975: 1-5 [doi]

Diversified Test Methods for Local Control UnitsChantal Robach, Gabriele Saucier. TC, 24(5):562-567, 1975.

1972

Next-State Equations of Asynchronous Sequential MachinesGabriele Saucier. TC, 21(4):397-399, 1972. [doi]

State Assignment of Asynchronous Sequential Machines Using Graph TechniquesGabriele Saucier. TC, 21(3):282-288, 1972. [doi]

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