Table of Contents

• A Regularly Structured 54-bit Modified-Wallace-Tree MultiplierT. Sato, M. Nakajima, T. Sukemura, G. Goto. 1-10
• OCAPI: A Prototype for High Precision ArithmeticAlain Guyot, Y. Kusumaputri. 11-18
• Design of a Highly Pipelined 2nd Order IIR Filter ChipO. C. McNally, John V. McCanny, Roger F. Woods. 19-28
• Design of a Fully Parallel Viterbi DecoderJens Sparsø, Steen Pedersen, Erik Paaske. 29-38
• Pipelined BIT-Serial SYNthesis of Digital Filerting AlgorithmsR. Nagalla, Laurence E. Turner. 39-48
• Symbolic Model Checking with Partitioned Transistion RelationsJerry R. Burch, Edmund M. Clarke, David E. Long. 49-58
• Integration of Formal Methods with System DesignEleanor M. Mayger, Michael P. Fourman. 59-69
• Deriving Bit-Serial Circuits in RubyGeraint Jones, Mary Sheeran. 71-80
• Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order EnvironmentKlaus Schneider, Ramayya Kumar, Thomas Kropf. 81-90
• DOMINO: Deterministic Placement Improvement with Hill-Climbing CapabilitiesKonrad Doll, Frank M. Johannes, Georg Sigl. 91-100
• A Flow-Oriented Approach to the Placement of Boolean NetworksStefan Mayrhofer, Massoud Pedram, Ulrich Lauther. 101-110
• Bounds on Net Delays for Physical Design of Fast CircuitsHabib Youssef, Rung-Bin Lin, Eugene Shragowitz. 111-118
• Area Minimisation of IC Power/Ground Nets by Topology OptimisationKarl-Heinz Erhard, Frank M. Johannes. 119-126
• On Distributed Logic Simulation Using Time WarpHerbert Bauer, Christian Sporrer, Thomas H. Krodel. 127-136
• An Integrated Environment for the Design and Simulation of Self-Timed SystemsErik Brunvand, M. Starkey. 137-146
• A General Purpose Network Solving SystemTom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski. 147-156
• On-Chip CMOS Sensors for VLSI Imaging SystemsPeter B. Denyer, David S. Renshaw, Gouyu Wang, Ming Ying Lu, Stuart Anderson. 157-166
• A Customizable Neural Processor for Distributed Neural NetworkJ. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, L. Masse-Navette. 167-176
• A VLSI Module for Analog Adaptive Neural ArchitecturesDaniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio. 177-186
• Has CAD for VLSI Reached a Dead End?A. Richard Newton. 187-192
• Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput ApplicationsWerner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man. 193-202
• A New Approach to Multiplexer Minimisation in the CALLAS Synthesis EnvironmentNorbert Wehn, J. Biesenack, Michael Pilsl. 203-213
• Meta VHDL for Higher Level Controller Modeling and SynthesisAhmed Amine Jerraya, Pierre G. Paulin, Simon Curry. 215-224
• Towards a Formal Model of VLSI Systems Compativle with VHDLPhilip A. Wilsey, Timothy J. McBrayer, David Sims. 225-236
• Hardware Design Using CASE ToolsWolfgang Glunz, Gerd Venzl. 237-246
• A VLSI System Design for the Control of High Performance Combustion EnginesA. Laudenbach, Manfred Glesner, Norbert Wehn. 247-256
• A Fully Integrated Systolic Spelling Co-ProcessorPatrice Frison, Dominique Lavenier. 257-266
• Parallel Architecture and VLSI Implementation of a 80MHz 2D-DCT 80 MHz 2D-DCT/ICDT ProcessorWolfram Liebsch, K. Boettcher. 267-275
• Exact Redundant State Registers Removal Based on Binary Decision DiagramsBill Lin, A. Richard Newton. 277-286
• Resources Restricted Global SchedulingP. F. Yeung, D. J. Rees. 287-296
• Synthesis of Intermediate Memories needed for the Data Supply to Processor ArraysMirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch. 297-306
• Workspace and Methodology Management in the Octtools EnvironmentMarina Zanella, Paolo Gubian. 307-316
• Single-Level Wiring for CMOS Functional CellsJan Madsen. 317-326
• An Over-the-Cell Channel RouterRavi R. Pai, S. S. S. P. Rao. 327-336
• Switchbox Routing by Pattern MatchingM. Starkey, Tony M. Carter. 337-346
• GPFP: A SIMD PE for Higher VLSI DensitiesDonald F. Beal, Costas Lambrinoudakis. 347-356
• Input/Output Design for VLSI Array ArchitecturesWayne P. Burleson, Louis L. Scharf. 357-366
• Comparing Transformation Schemes for VLSI Array Processor Design - A Case StudyAnders Færgemand Nielsen, Poul Martin Rands Jensen, Kallol Kumar Bagchi, Ole Olsen. 367-376
• A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical InterconnectionsMitsumasa Koyanagi. 377-386
• Pass-Transistor Self-Clocked Asynchronous Sequential CircuitsFarhad Aghdasi. 387-395
• Theoretical and Practical Issues in CMOS Wave PipeliningC. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III. 397-409
• Automatic Interfacing of Synchronous Modules to an Asynchronous EnvironmentNaser Awad, David R. Smith. 411-420
• How to Compare Analog ResultsBernhard Klaassen. 421-428
• Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI ComponentsBulent I. Dervisoglu, Gayvin E. Stong. 429-438
• Identification and Resynthesis of Pipelines in Sequential NetworksSujit Dey, Franc Brglez, Gershon Kedem. 439-449
• Hierarchical Retiming Including PipeliningAlbert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh. 451-460
• Preserving Don t Care Conditions During RetimingEllen Sentovich, Robert K. Brayton. 461-470
• A Fault Tolerant and High Speed Instruction Systolic ArrayManfred Schimmler, Hartmut Schmeck. 471-480
• A Reconfigurable Fault Tolerant Module Approach to the Reliability Enhancement for Mesh Connected Processor ArraysGuoning Liao. 481-490
• The WASP 2 Wafer Scale Integration DemonstratorIan P. Jalowiecki, Stephen J. Hedge. 491-500